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| CY7C601xx, CY7C602xx enCoReTM II Low Voltage Microcontroller 1. Features enCoReTM II Low Voltage (enCoRe II LV)--enhanced component reduction Internal crystalless oscillator with support for optional external clock or external crystal or resonator Configurable IO for real world interface without external components Enhanced 8-bit microcontroller Harvard architecture M8C CPU speed up to 12 MHz or sourced by an external crystal, resonator, or clock signal Internal memory 256 bytes of RAM 8 Kbytes of Flash including EEROM emulation Low power consumption Typically 2.25 mA at 3 MHz 5 A sleep In-system reprogrammability Allows easy firmware update General purpose IO ports Up to 36 General Purpose IO (GPIO) pins 2 mA source current on all GPIO pins. Configurable 8 or 50 mA per pin current sink on designated pins Each GPIO port supports high impedance inputs, configurable pull up, open drain output, CMOS and TTL inputs, and CMOS output Maskable interrupts on all IO pins SPI serial communication Master or slave operation Configurable up to 2 Mbit per second transfers Supports half duplex single data line mode for optical sensors 2-channel 8-bit or 1-channel 16-bit capture timer registers. Capture timer registers store both rising and falling edge times Two registers each for two input pins Separate registers for rising and falling edge capture Simplifies interface to RF inputs for wireless applications Internal low power wakeup timer during suspend mode Periodic wakeup with no external components Programmable interval timer interrupts Reduced RF emissions at 27 MHz and 96 MHz Watchdog timer (WDT) Low voltage detection with user selectable threshold voltages Improved output drivers to reduce EMI Operating voltage from 2.7V to 3.6V DC Operating temperature from 0-70C Available in 24 and 40-pin PDIP, 24-pin SOIC, 24-pin QSOP and SSOP, 28-pin SSOP, and 48-pin SSOP Advanced development tools based on Cypress PSoC(R) tools Industry standard programmer support 2. Logic Block Diagram Interrupt Control 4 SPI/GPIO Pins 16 Extended I/O Pins 16 GPIO Pins Wakeup Timer Internal 12 MHz Oscillator Clock Control Crystal Oscillator CY7C601xx only M8C CPU RAM 256 Byte Flash 8K Byte Capture Timers 12-bit Timer POR / Low-Voltage Detect Vdd Watchdog Timer Cypress Semiconductor Corporation Document 38-16016 Rev. *E * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised December 08, 2008 [+] Feedback CY7C601xx, CY7C602xx 3. Applications The CY7C601xx and CY7C602xx are targeted for the following applications: PC wireless HID devices Mice (optomechanical, optical, trackball) Keyboards Presenter tools Gaming Joysticks Gamepad General purpose wireless applications Remote controls Barcode scanners POS terminal Consumer electronics Toys In addition, enCoRe II LV includes a watchdog timer, a vectored interrupt controller, a 16-bit free running timer with capture registers, and a 12-bit programmable interval timer. The power on reset circuit detects when power is applied to the device, resets the logic to a known state, and executes instructions at Flash address 0x0000. When power falls below a programmable trip voltage, it generates a reset or is configured to generate an interrupt. There is a low voltage detect circuit that detects when VCC drops below a programmable trip voltage. This is configurable to generate a LVD interrupt to inform the processor about the low voltage event. POR and LVD share the same interrupt; there is no separate interrupt for each. The watchdog timer ensures the firmware never gets stalled in an infinite loop. The microcontroller supports 17 maskable interrupts in the vectored interrupt controller. All interrupts can be masked. Interrupt sources include LVR or POR, a programmable interval timer, a nominal 1.024 ms programmable output from the free running timer, two capture timers, five GPIO ports, three GPIO pins, two SPI, a 16-bit free running timer wrap, and an internal wakeup timer interrupt. The wakeup timer causes periodic interrupts when enabled. The capture timers interrupt whenever a new timer value is saved due to a selected GPIO edge event. A total of eight GPIO interrupts support both TTL or CMOS thresholds. For additional flexibility, on the edge-sensitive GPIO pins, the interrupt polarity is programmable to be either rising or falling. The free running timer generates an interrupt at 1024 s rate. It also generates an interrupt when the free running counter overflow occurs--every 16.384 ms. The duration of an event under firmware control is measured by reading the timer at the start and end of an event, then calculating the difference between the two values. The two 8-bit capture timer registers save a programmable 8-bit range of the free running timer when a GPIO edge occurs on the two capture pins (P0.5 and P0.6). The two 8-bit capture registers are ganged into a single 16-bit capture register. The enCoRe II LV supports in-system programming by using the P1.0 and P1.1 pins as the serial programming mode interface. 4. Introduction The enCoRe II LV family brings the features and benefits of the enCoRe II to non USB applications. The enCoRe II family has an integrated oscillator that eliminates the external crystal or resonator, reducing overall cost. Other external components, such as wakeup circuitry, are also integrated into this chip. The enCoRe II LV is a low voltage, low cost 8-bit Flash programmable microcontroller. The enCoRe II LV features up to 36 GPIO pins. The IO pins are grouped into five ports (Port 0 to 4). The pins on Ports 0 and 1 are configured individually, when the pins on Ports 2, 3, and 4 are only configured as a group. Each GPIO port supports high impedance inputs, configurable pull up, open drain output, CMOS and TTL inputs, and CMOS output with up to five pins that support programmable drive strength of up to 50 mA sink current. Additionally, each IO pin is used to generate a GPIO interrupt to the microcontroller. Each GPIO port has its own GPIO interrupt vector with the exception of GPIO Port 0. GPIO Port 0 has, in addition to the port interrupt vector, three dedicated pins that have independent interrupt vectors (P0.2-P0.4). The enCoRe II LV features an internal oscillator. Optionally, an external 1 MHz to 24 MHz crystal is used to provide a higher precision reference. The enCoRe II LV also supports external clock. The enCoRe II LV has 8 Kbytes of Flash for user code and 256 bytes of RAM for stack space and user variables. 5. Conventions In this document, bit positions in the registers are shaded to indicate which members of the enCoRe II LV family implement the bits. Available in all enCoRe II LV family members CY7C601xx only Document 38-16016 Rev. *E Page 2 of 68 [+] Feedback CY7C601xx, CY7C602xx 6. Pinouts Figure 6-1. Package Configurations Top View CY7C60223 24-Pin PDIP P3.0 P3.1 SCLK/P1.4 SMOSI/P1.5 SMISO/P1.6 P1.7 NC NC P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 P1.3/SSEL P1.2 VDD P1.1 P1.0 VSS P2.0 P2.1 P0.0/CLKIN P0.1/CLKOUT P0.2/INT0 P0.3/INT1 CY7C60223 24-Pin SOIC NC P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 CLKOUT\P0.1 CLKIN\P0.0 P2.1 P2.0 VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 NC P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P3.1 P3.0 P1.3/SSEL P1.2 VDD P1.1 P1.0 CY7C60223 24-Pin QSOP NC P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 CLKOUT\P0.1 CLKIN\P0.0 P2.1 P2.0 NC 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P3.1 P3.0 P1.3/SSEL P1.2 VDD P1.1 P1.0 VSS CY7C60113 28-Pin SSOP VDD P2.7 P2.6 P2.5 P2.4 P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 CLKOUT/P0.1 CLKIN/P0.0 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS P3.7 P3.6 P3.5 P3.4 P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P1.3/SSEL P1.2 VDD P1.1 P1.0 CY7C60123 40-Pin PDIP VDD P4.1 P4.0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P0.7 T1O1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 CLKOUT/P0.1 CLKIN/P0.0 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS P4.3 P4.2 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P1.3/SSEL P1.2 VDD P1.1 P1.0 CY7C60123 48-Pin SSOP NC NC NC NC VDD P4.1 P4.0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P0.7 TIO1/P0.6 TIO0/PO.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 CLKOUT/P0.1 CLKIN/P0.0 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC NC NC VSS P4.3 P4.2 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P1.3/SSEL P1.2 VDD P1.1 P1.0 Document 38-16016 Rev. *E Page 3 of 68 [+] Feedback CY7C601xx, CY7C602xx 6.1 Pin Assignments Table 6-1. Pin Assignments 48 40 28 24 24 SSOP PDIP SSOP QSOP SOIC 7 6 42 43 34 35 36 37 38 39 40 41 15 14 13 12 11 10 9 8 25 3 2 38 39 30 31 32 33 34 35 36 37 11 10 9 8 7 6 5 4 21 5 4 3 2 15 14 13 20 24 25 26 27 11 10 11 10 18 17 19 20 18 19 1 2 24 PDIP Name P4.0 P4.1 P4.2 P4.3 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P1.0 GPIO Port 1 bit 0 If this pin is used as a general purpose output it draws current. It is, therefore, configured as an input to reduce current draw. GPIO Port 1 bit 1 If this pin is used as a general purpose output it draws current. It is, therefore, configured as an input to reduce current draw. GPIO Port 1 bit 2 GPIO Port 1 bit 3--Configured individually Alternate function is SSEL signal of the SPI bus. GPIO Port 1 bit 4--Configured individually Alternate function is SCLK signal of the SPI bus. GPIO Port 1 bit 5--Configured individually Alternate function is SMOSI signal of the SPI bus. GPIO Port 1 bit 6--Configured individually Alternate function is SMISO signal of the SPI bus. GPIO Port 1 bit 7--Configured individually TTL voltage threshold. GPIO Port 2--configured as a group (byte) GPIO Port 3--configured as a group (byte) Description GPIO Port 4--configured as a group (nibble) 26 22 16 15 14 21 P1.1 28 29 30 31 32 33 24 25 26 27 28 29 18 19 20 21 22 23 17 18 21 22 23 24 16 17 20 21 22 23 23 24 3 4 5 6 P1.2 P1.3/SSEL P1.4/SCLK P1.5/SMOSI P1.6/SMISO P1.7 Document 38-16016 Rev. *E Page 4 of 68 [+] Feedback CY7C601xx, CY7C602xx Table 6-1. Pin Assignments (continued) 48 40 28 24 24 SSOP PDIP SSOP QSOP SOIC 23 19 13 9 9 24 PDIP 16 Name P0.0/CLKIN Description GPIO Port 0 bit 0--Configured individually On CY7C601xx, optional Clock In when external oscillator is disabled or external oscillator input when external oscillator is enabled. On CY7C602xx, oscillator input when configured as Clock In. 22 18 12 8 8 15 P0.1/CLKOUT GPIO Port 0 bit 1--Configured individually On CY7C601xx, optional Clock Out when external oscillator is disabled or external oscillator output drive when external oscillator is enabled. On CY7C602xx, oscillator output when configured as Clock Out. P0.2/INT0 P0.3/INT1 P0.4/INT2 P0.5/TIO0 P0.6/TIO1 P0.7 NC NC VDD GPIO port 0 bit 2--Configured individually Optional rising edge interrupt INT0. GPIO port 0 bit 3--Configured individually Optional rising edge interrupt INT1. GPIO port 0 bit 4--Configured individually Optional rising edge interrupt INT2. GPIO port 0 bit 5--Configured individually Alternate function timer capture inputs or timer output TIO0. GPIO port 0 bit 6--Configured individually Alternate function timer capture inputs or timer output TIO1. GPIO port 0 bit 7--Configured individually No connect No connect Power Ground 21 20 19 18 17 16 1,2,3, 4 45,46, 47,48 5 27 44 24 17 16 15 14 13 12 11 10 9 8 7 6 7 6 5 4 3 2 1 12 7 6 5 4 3 2 1 24 14 13 12 11 10 9 7 8 1 23 40 20 17 1 14 28 16 - 13 15 - 12 22 - 19 VSS Document 38-16016 Rev. *E Page 5 of 68 [+] Feedback CY7C601xx, CY7C602xx 7. Register Summary Table 7-1. enCoRe II LV Register Summary The XIO bit in the CPU Flags Register must be set to access the extended register space for all registers above 0xFF. Addr 00 01 02 03 04 05 06 07-09 0A-0B 0C 0D 0E 0F 10 11-13 14 15 16 17 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 30 31 32 Name P0DATA P1DATA P2DATA P3DATA P4DATA P00CR P01CR P02CR- P04CR P05CR- P06CR P07CR P10CR P11CR P12CR P13CR P14CR- P16CR P17CR P2CR P3CR P4CR FRTMRL FRTMRH TCAP0R TCAP1R TCAP0F TCAP1F PITMRL PITMRH PIRL PIRH TMRCR TCAPINTE TCAPINTS CPUCLKCR TMRCLKCR CLKIOCR 7 P0.7 P1.7 6 P0.6/TIO1 5 P0.5/TIO0 4 P0.4/INT2 P1.4/SCLK 3 P0.3/INT1 P1.3/SSEL 2 P0.2/INT0 P1.2 1 P0.1/ CLKOUT P1.1 0 P0.0/CLKIN P1.0 R/W bbbbbbbb bbbbbbbb bbbbbbbb bbbbbbbb ----bbbb Default 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 10001111 00000000 P1.6/SMISO P1.5/SMOSI P2.7-P2.2 P3.7-P3.2 Reserved Reserved CLK Output Int Enable Int Enable Int Act Low Int Act Low Int Act Low Int Act Low Int Act Low Int Act Low Int Act Low Int Act Low Int Act Low Int Act Low Int Act Low Int Act Low Int Act Low Int Act Low Reserved TTL Threshold Reserved Reserved Reserved TTL Thresh TTL Thresh TTL Thresh Reserved High Sink High Sink High Sink High Sink High Sink Reserved TTL Thresh TTL Thresh TTL Thresh TTL Thresh TTL Thresh High Sink High Sink Reserved Reserved Reserved P4.3-P4.0 Open Drain Open Drain Open Drain Open Drain Open Drain P2.1-P2.0 P3.1-P3.0 Pull up Enable Pull Up Enable Pull Up Enable Pull Up Enable Pull Up Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable -bbbbbbb bbbbbbbb --bb-bbb bbbb-bbb -bbb-bbb -bb----b -bb--b-b bbbb-bbb -bb-bbbb bbb-bbbb -bb-bbbb -bbbbbbb -bbbbbbb -bbb-bbb bbbbbbbb bbbbbbbb rrrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr Reserved TIO Output Reserved Reserved Reserved CLK Output Reserved SPI Use Reserved Reserved Reserved Reserved Int Enable Int Enable Int Enable Int Enable Int Enable Int Enable Int Enable Int Enable Int Enable Int Enable Int Enable Reserved Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Reserved Pull Up Enable Pull Up Enable Pull Up Enable Pull Up Enable Pull Up Enable Pull Up Enable Pull Up Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Free Running Timer [7:0] Free Running Timer [15:8] Capture 0 Rising [7:0] Capture 1 Rising [7:0] Capture 0 Falling [7:0] Capture 1 Falling [7:0] Prog Interval Timer [7:0] Reserved Prog Interval [7:0] Reserved First Edge Hold 8-bit Capture Prescale Reserved Reserved Reserved TCAPCLK Divider Reserved TCAPCLK Select XOSC Select ITMRCLK Divider XOSC Enable EFTB Disabled Cap0 16-bit Enable Cap1 Fall Active Cap1 Fall Active Cap1 Rise Active Cap1 Rise Active Prog Interval [11:8] Reserved Cap0 Fall Active Cap0 Fall Active Cap0 Rise Active Cap0 Rise Active CPU CLK Select ITMRCLK Select CLKOUT Select Prog Interval Timer [11:8] ----rrrr bbbbbbbb ----bbbb bbbbb------bbbb ----bbbb -------b bbbbbbbb ---bbbbb Document 38-16016 Rev. *E Page 6 of 68 [+] Feedback CY7C601xx, CY7C602xx Table 7-1. enCoRe II LV Register Summary (continued) The XIO bit in the CPU Flags Register must be set to access the extended register space for all registers above 0xFF. Addr 34 35 36 3C 3D DA DB DC Name IOSCTR XOSCTR LPOSCTR SPIDATA SPICR 7 6 foffset[2:0] Reserved 5 4 3 XOSC XGM [2:0] 2 Gain[4:0] 1 Reserved 0 Mode R/W bbbbbbbb ---bbb-b b-bbbbbb bbbbbbbb Default 000ddddd 000ddddd d-dddddd 00000000 00000000 00000000 00000000 00000000 32 kHz Low Power Reserved 32 kHz Bias Trim [1:0] SPIData[7:0] 32 kHz Freq Trim [3:0] Swap LSB First Comm Mode INT1 GPIO Port 0 CPOL SPI Receive CPHA SPI Transmit Reserved SCLK Select INT0 POR/LVD bbbbbbbb bbbbbbbb bbb----- INT_CLR0 GPIO Port 1 Sleep Timer INT_CLR1 INT_CLR2 TCAP0 Reserved Prog Interval 1 ms Timer Timer GPIO Port 4 GPIO Port 3 GPIO Port 2 Reserved INT2 16-bit Counter Wrap TCAP1 -bbb-bbb DE DF INT_MSK3 INT_MSK2 ENSWINT Reserved GPIO Port 4 GPIO Port 3 GPIO Port 2 Int Enable Int Enable Int Enable Reserved Reserved INT2 Int Enable 16-bit Counter Wrap Int Enable TCAP1 Int Enable r-------bbb-bbb 00000000 00000000 E1 INT_MSK1 TCAP0 Prog Interval 1 ms Timer Int Enable Timer Int Enable Int Enable INT1 Int Enable GPIO Port 0 Int Enable SPI Receive Int Enable Reserved bbb----- 00000000 E0 E2 E3 -----F7 FF 1E0 1E3 1EB 1E4 INT_MSK0 GPIO Port 1 Sleep Timer Int Enable Int Enable INT_VC RESWDT CPU_A CPU_X CPU_PCL CPU_PCH CPU_SP CPU_F CPU_SCR OSC_CR0 LVDCR ECO_TR VLTCMP GIES Reserved Reserved SPI Transmit Int Enable INT0 Int Enable POR/LVD Int Enable bbbbbbbb bbbbbbbb wwwwwww w ------------------------------------ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000010 00010100 00000000 00000000 00000000 00000000 Pending Interrupt [7:0] Reset Watchdog Timer [7:0] Temporary Register T1 [7:0] X[7:0] Program Counter [7:0] Program Counter [15:8] Stack Pointer [7:0] XIO WDRS No Buzz PORS Super Sleep Carry Reserved Zero Reserved CPU Speed [2:0] VM[2:0] Global IE Stop ---brbbb r-ccb--b --bbbbbb --bb-bbb bb------ Reserved Reserved Sleep Duty Cycle [1:0] Sleep Timer [1:0] Reserved Reserved Reserved PORLEV[1:0] LVD PPOR ------rr Note In the R/W column: b = Both Read and Write r = Read Only w = Write Only c = Read or Clear d = Calibration Value. Must not change during normal use Document 38-16016 Rev. *E Page 7 of 68 [+] Feedback CY7C601xx, CY7C602xx 8. CPU Architecture This family of microcontrollers is based on a high performance, 8-bit, Harvard architecture microprocessor. Five registers control the primary operation of the CPU core. These registers are affected by various instructions, but are not directly accessible through the register space by the user. Table 8-1. CPU Registers and Register Name Register Flags Program Counter Accumulator Stack Pointer Index Register Name CPU_F CPU_PC CPU_A CPU_SP CPU_X The Accumulator Register (CPU_A) is the general purpose register that holds results of instructions that specify any of the source addressing modes. The Index Register (CPU_X) holds an offset value used in the indexed addressing modes. Typically, this is used to address a block of data within the data memory space. The Stack Pointer Register (CPU_SP) holds the address of the current top-of-stack in the data memory space. It is affected by the PUSH, POP, LCALL, CALL, RETI, and RET instructions, which manage the software stack. It is also affected by the SWAP and ADD instructions. The Flag Register (CPU_F) has three status bits: Zero Flag bit [1]; Carry Flag bit [2]; Supervisory State bit [3]. The Global Interrupt Enable bit [0] is used to globally enable or disable interrupts. The user cannot manipulate the Supervisory State status bit [3]. The flags are affected by arithmetic, logic, and shift operations. The manner in which each flag is changed is dependent upon the instruction being executed (AND, OR, XOR). See Table 10-1. The 16-bit Program Counter Register (CPU_PC) directly addresses the full 8 Kbytes of program memory space. 9. CPU Registers 9.1 Flags Register The Flags Register is only set or reset with logical instruction. Table 9-1. CPU Flags Register (CPU_F) [R/W] Bit # Field Read/Write Default - 0 7 6 Reserved - 0 - 0 5 4 XIO R/W 0 3 Super R 0 2 Carry R/W 0 1 Zero R/W 1 0 Global IE R/W 0 Bit [7:5]: Reserved Bit 4: XIO Set by the user to select between the register banks. 0 = Bank 0 1 = Bank 1 Bit 3: Super Indicates whether the CPU is executing user code or supervisor code. (This code cannot be accessed directly by the user.) 0 = User Code 1 = Supervisor Code Bit 2: Carry Set by CPU to indicate whether there is a carry in the previous logical or arithmetic operation. 0 = No Carry 1 = Carry Bit 1: Zero Set by CPU to indicate whether there is a zero result in the previous logical or arithmetic operation. 0 = Not Equal to Zero 1 = Equal to Zero Bit 0: Global IE Determines whether all interrupts are enabled or disabled. 0 = Disabled 1 = Enabled Note This register is readable with explicit address 0xF7. The OR F, expr and AND F, expr are used to set and clear the CPU_F bits. Document 38-16016 Rev. *E Page 8 of 68 [+] Feedback CY7C601xx, CY7C602xx 9.1.1 Accumulator Register Table 9-2. CPU Accumulator Register (CPU_A) Bit # Field Read/Write Default - 0 - 0 - 0 7 6 5 4 3 2 1 0 CPU Accumulator [7:0] - 0 - 0 - 0 - 0 - 0 Bit [7:0]: CPU Accumulator [7:0] 8-bit data value holds the result of any logical or arithmetic instruction that uses a source addressing mode. 9.1.2 Index Register Table 9-3. CPU X Register (CPU_X) Bit # Field Read/Write Default - 0 - 0 - 0 - 0 7 6 5 4 X [7:0] - 0 - 0 - 0 - 0 3 2 1 0 Bit [7:0]: X [7:0] 8-bit data value holds an index for any instruction that uses an indexed addressing mode. 9.1.3 Stack Pointer Register Table 9-4. CPU Stack Pointer Register (CPU_SP) Bit # Field Read/Write Default - 0 - 0 - 0 7 6 5 4 3 2 1 0 Stack Pointer [7:0] - 0 - 0 - 0 - 0 - 0 Bit [7:0]: Stack Pointer [7:0] 8-bit data value holds a pointer to the current top-of-stack. 9.1.4 CPU Program Counter High Register Table 9-5. CPU Program Counter High Register (CPU_PCH) Bit # Field Read/Write Default - 0 - 0 - 0 7 6 5 4 3 2 1 0 Program Counter [15:8] - 0 - 0 - 0 - 0 - 0 Bit [7:0]: Program Counter [15:8] 8-bit data value holds the higher byte of the program counter. 9.1.5 CPU Program Counter Low Register Table 9-6. CPU Program Counter Low Register (CPU_PCL) Bit # Field Read/Write Default - 0 - 0 - 0 7 6 5 4 3 2 1 0 Program Counter [7:0] - 0 - 0 - 0 - 0 - 0 Bit [7:0]: Program Counter [7:0] 8-bit data value holds the lower byte of the program counter. Document 38-16016 Rev. *E Page 9 of 68 [+] Feedback CY7C601xx, CY7C602xx 9.2 Addressing Modes 9.2.1 Source Immediate The result of an instruction using this addressing mode is placed in the A register, the F register, the SP register, or the X register, which is specified as part of the instruction opcode. Operand 1 is an immediate value that serves as a source for the instruction. Arithmetic instructions require two sources; the second source is the A, X, SP, or F register specified in the opcode. Instructions using this addressing mode are two bytes in length. Table 9-7. Source Immediate Opcode Instruction Examples ADD A, 7 ;In this case, the immediate value of 7 is added with the Accumulator and the result is placed in the Accumulator. ;In this case, the immediate value of 8 is moved to the X register. ;In this case, the immediate value of 9 is logically ANDed with the F register and the result is placed in the F register. MOV X, REG[X+8] 9.2.3 Source Indexed The result of an instruction using this addressing mode is placed in either the A register or the X register, which is specified as part of the instruction opcode. Operand 1 is added to the X register forming an address that points to a location in either the RAM memory space or the register space that is the source for the instruction. Arithmetic instructions require two sources; the second source is the A register or X register specified in the opcode. Instructions using this addressing mode are two bytes in length. Table 9-9. Source Indexed Opcode Instruction Examples ADD A, [X+7] ;In this case, the value in the memory location at address X + 7 is added with the Accumulator, and the result is placed in the Accumulator. ;In this case, the value in the register space at address X + 8 is moved to the X register. Operand 1 Immediate Value Operand 1 Source Index MOV AND X, F, 8 9 9.2.2 Source Direct The result of an instruction using this addressing mode is placed in either the A register or the X register, which is specified as part of the instruction opcode. Operand 1 is an address that points to a location in either the RAM memory space or the register space that is the source for the instruction. Arithmetic instructions require two sources; the second source is the A register or X register specified in the opcode. Instructions using this addressing mode are two bytes in length. Table 9-8. Source Direct Opcode Instruction Examples ADD A, [7] ;In this case, the value in the RAM memory location at address 7 is added with the Accumulator, and the result is placed in the Accumulator. ;In this case, the value in the register space at address 8 is moved to the X register. 9.2.4 Destination Direct The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is an address that points to the location of the result. The source for the instruction is either the A register or the X register, which is specified as part of the instruction opcode. Arithmetic instructions require two sources; the second source is the location specified by Operand 1. Instructions using this addressing mode are two bytes in length. Table 9-10. Destination Direct Operand 1 Source Address Opcode Instruction Examples ADD [7], A Operand 1 Destination Address MOV X, REG[8] ;In this case, the value in the memory location at address 7 is added with the Accumulator, and the result is placed in the memory location at address 7. The Accumulator is unchanged. ;In this case, the Accumulator is moved to the register space location at address 8. The Accumulator is unchanged. MOV REG[8], A Document 38-16016 Rev. *E Page 10 of 68 [+] Feedback CY7C601xx, CY7C602xx 9.2.5 Destination Indexed The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is added to the X register forming the address that points to the location of the result. The source for the instruction is the A register. Arithmetic instructions require two sources; the second source is the location specified by Operand 1 added with the X register. Instructions using this addressing mode are two bytes in length. Table 9-11. Destination Indexed Opcode Instruction Example ADD [X+7], A ;In this case, the value in the memory location at address X+7 is added with the Accumulator and the result is placed in the memory location at address X+7. The Accumulator is unchanged. 9.2.7 Destination Indexed Source Immediate The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is added to the X register to form the address of the result. The source for the instruction is Operand 2, which is an immediate value. Arithmetic instructions require two sources; the second source is the location specified by Operand 1 added with the X register. Instructions using this addressing mode are three bytes in length. Table 9-13. Destination Indexed Source Immediate Operand 1 Opcode Instruction Examples ADD [X+7], 5 ;In this case, the value in the memory location at address X+7 is added with the immediate value of 5, and the result is placed in the memory location at address X+7. ;In this case, the immediate value of 6 is moved into the location in the register space at address X+8. Operand 1 Destination Index Operand 2 Immediate Value Destination Index MOV REG[X+8], 6 9.2.6 Destination Direct Source Immediate The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is the address of the result. The source for the instruction is Operand 2, which is an immediate value. Arithmetic instructions require two sources; the second source is the location specified by Operand 1. Instructions using this addressing mode are three bytes in length. Table 9-12. Destination Direct Source Immediate Opcode Instruction Examples ADD [7], 5 ;In this case, value in the memory location at address 7 is added to the immediate value of 5, and the result is placed in the memory location at address 7. ;In this case, the immediate value of 6 is moved into the register space location at address 8. 9.2.8 Destination Direct Source Direct The result of an instruction using this addressing mode is placed within the RAM memory. Operand 1 is the address of the result. Operand 2 is an address that points to a location in the RAM memory that is the source for the instruction. This addressing mode is only valid on the MOV instruction. The instruction using this addressing mode is three bytes in length. Table 9-14. Destination Direct Source Direct Opcode Instruction Example MOV [7], [8] ;In this case, the value in the memory location at address 8 is moved to the memory location at address 7. Operand 1 Destination Address Operand 2 Immediate Value Operand 1 Destination Address Operand 2 Source Address MOV REG[8], 6 Document 38-16016 Rev. *E Page 11 of 68 [+] Feedback CY7C601xx, CY7C602xx 9.2.9 Source Indirect Post Increment The result of an instruction using this addressing mode is placed in the Accumulator. Operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the source of the instruction. The indirect address is incremented as part of the instruction execution. This addressing mode is only valid on the MVI instruction. The instruction using this addressing mode is two bytes in length. Refer to the PSoC Designer: Assembly Language User Guide for further details on MVI instruction. Table 9-15. Source Indirect Post Increment Opcode Instruction Example MVI A, [8] ;In this case, the value in the memory location at address 8 is an indirect address. The memory location pointed to by the Indirect address is moved into the Accumulator. The indirect address is then incremented. 9.2.10 Destination Indirect Post Increment The result of an instruction using this addressing mode is placed within the memory space. Operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the destination of the instruction. The indirect address is incremented as part of the instruction execution. The source for the instruction is the Accumulator. This addressing mode is only valid on the MVI instruction. The instruction using this addressing mode is two bytes in length. Table 9-16. Destination Indirect Post Increment Opcode Instruction Example MVI [8], A ;In this case, the value in the memory location at address 8 is an indirect;address. The Accumulator is moved into the memory location pointed to by the indirect address. The indirect address is then incremented. Operand 1 Destination Address Address Operand 1 Source Address Address 10. Instruction Set Summary The instruction set is summarized in Table 10-1 numerically and serves as a quick reference. For more information, the Instruction Set Summary tables are described in detail in the PSoC Designer Assembly Language User Guide (available on the www.cypress.com web site). Table 10-1. Instruction Set Summary Sorted Numerically by Opcode Order Opcode Hex Opcode Hex Opcode Hex Cycles Cycles Cycles Bytes Bytes Instruction Format[1, 2] Bytes Flags Instruction Format Flags Instruction Format Flags 00 15 1 01 4 02 6 03 7 04 7 05 8 06 9 08 2 2 2 2 2 3 SSC ADD A, expr ADD A, [expr] ADD A, [X+expr] ADD [expr], A ADD [X+expr], A ADD [expr], expr ADD [X+expr], expr PUSH A ADC A, expr ADC A, [expr] ADC A, [X+expr] ADC [expr], A ADC [X+expr], A ADC [expr], expr ADC [X+expr], expr PUSH X SUB A, expr SUB A, [expr] C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z 2D 8 2E 9 30 2 3 OR [X+expr], A OR [expr], expr OR [X+expr], expr HALT XOR A, expr XOR A, [expr] XOR A, [X+expr] XOR [expr], A XOR [X+expr], A XOR [expr], expr XOR [X+expr], expr ADD SP, expr CMP A, expr CMP A, [expr] CMP A, [X+expr] CMP [expr], expr CMP [X+expr], expr MVI A, [ [expr]++ ] MVI [ [expr]++ ], A Z Z Z Z Z Z Z Z Z Z if (A=B) Z=1 if (A 2 1 1 2 2 2 2 3 3 MOV [expr], X MOV A, X MOV X, A MOV A, reg[expr] MOV A, reg[X+expr] MOV [expr], [expr] MOV reg[expr], A MOV reg[X+expr], A MOV reg[expr], expr MOV reg[X+expr], expr ASL A ASL [expr] ASL [X+expr] ASR A ASR [expr] ASR [X+expr] RLC A RLC [expr] RLC [X+expr] C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z Z Z Z 2F 10 3 91 2 2 2 2 2 3 31 4 32 6 33 7 34 7 35 8 36 9 5F 10 3 07 10 3 41 2 2 2 2 2 3 09 4 0A 6 0B 7 0C 7 0D 8 0E 9 10 11 12 37 10 3 38 39 52 52 41 72 82 41 72 82 3A 7 2 3B 8 2 3C 8 3 3D 9 3 3E 10 2 3F 10 2 0F 10 3 41 42 62 6A 4 1 Z 6B 7 2 6C 8 2 Document 38-16016 Rev. *E Page 12 of 68 [+] Feedback CY7C601xx, CY7C602xx Table 10-1. Instruction Set Summary Sorted Numerically by Opcode Order (continued) Opcode Hex Opcode Hex Opcode Hex Cycles Cycles Cycles Bytes Bytes Instruction Format[1, 2] Bytes Flags Instruction Format Flags Instruction Format Flags 13 14 15 16 18 19 72 72 82 93 51 42 SUB A, [X+expr] SUB [expr], A SUB [X+expr], A SUB [expr], expr SUB [X+expr], expr POP A SBB A, expr SBB A, [expr] SBB A, [X+expr] SBB [expr], A SBB [X+expr], A SBB [expr], expr SBB [X+expr], expr POP X AND A, expr AND A, [expr] AND A, [X+expr] AND [expr], A AND [X+expr], A AND [expr], expr AND [X+expr], expr ROMX OR A, expr OR A, [expr] OR A, [X+expr] OR [expr], A C, Z C, Z C, Z C, Z C, Z Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z Z Z Z Z Z Z Z Z Z Z Z Z 40 4 41 1 NOP AND reg[expr], expr AND reg[X+expr], expr OR reg[expr], expr XOR reg[expr], expr XOR reg[X+expr], expr TST [expr], expr TST [X+expr], expr TST reg[expr], expr SWAP A, X SWAP A, [expr] SWAP X, [expr] SWAP A, SP MOV X, SP MOV A, expr MOV A, [expr] MOV A, [X+expr] MOV [expr], A MOV [X+expr], A MOV [expr], expr MOV [X+expr], expr MOV X, expr MOV X, [expr] MOV X, [X+expr] Z Z Z Z Z Z Z Z Z Z Z Z Z Z 6D 4 1 6E 7 2 6F 8 2 70 72 73 74 75 76 77 78 79 42 2 42 41 41 41 72 82 41 41 RRC A RRC [expr] RRC [X+expr] AND F, expr OR F, expr XOR F, expr CPL A INC A INC X INC [expr] INC [X+expr] DEC A DEC X DEC [expr] DEC [X+expr] LCALL LJMP RETI RET JMP CALL JZ JNZ JC JNC JACC INDEX C, Z C, Z C, Z C, Z C, Z C, Z Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z 93 42 10 3 43 9 45 3 17 10 3 44 10 3 93 46 10 3 47 48 49 83 93 93 OR reg[X+expr], expr Z 71 4 1A 6 2 1B 7 2 1C 7 2 1D 8 2 1E 9 3 1F 10 3 20 21 22 23 24 25 26 51 42 62 72 72 82 93 4A 10 3 4B 5 1 4C 7 2 4D 7 2 4E 5 1 4F 4 50 4 51 5 52 6 53 5 54 6 55 8 56 9 57 4 58 6 59 7 1 2 2 2 2 2 3 3 2 2 2 TST reg[X+expr], expr Z 7A 7 2 7B 8 2 7C 13 3 7D 7 3 7E 10 1 7F 8 1 8x 52 2 2 2 2 2 9x 11 2 Ax 5 Bx 5 Cx 5 Dx 5 Ex 7 C, Z 27 10 3 28 11 1 29 4 2A 6 2B 7 2C 7 2 2 2 2 Fx 13 2 Z Notes 1. Interrupt routines take 13 cycles before execution resumes at interrupt vector table. 2. The number of cycles required by an instruction is increased by one for instructions that span 256 byte boundaries in the Flash memory space. Document 38-16016 Rev. *E Page 13 of 68 [+] Feedback CY7C601xx, CY7C602xx 11. Memory Organization 11.1 Flash Program Memory Organization Figure 11-1. Program Memory Space with Interrupt Vector Table after reset 16-bit PC Address 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 Program execution begins here after a reset POR/LVD INT0 SPI Transmitter Empty SPI Receiver Full GPIO Port 0 GPIO Port 1 INT1 Reserved Reserved Reserved Reserved Reserved 1 ms Interval timer Programmable Interval Timer Timer Capture 0 Timer Capture 1 16-bit Free Running Timer Wrap INT2 Reserved GPIO Port 2 GPIO Port 3 GPIO Port 4 Reserved Reserved Sleep Timer Program Memory begins here (if below interrupts not used, program memory can start lower) 0x1FFF Document 38-16016 Rev. *E Page 14 of 68 [+] Feedback CY7C601xx, CY7C602xx 11.2 Data Memory Organization The CY7C601xx and CY7C602xx microcontrollers provide up to 256 bytes of data RAM Figure 11-2. Data Memory Organization After Reset 8-bit PSP Address 0x00 Stack begins here and grows upward Top of RAM Memory 0xFF 11.3 Flash This section describes the Flash block of enCoRe II LV. Much of the visible Flash functionality, including programming and security, are implemented in the M8C Supervisory Read Only Memory (SROM). enCoRe II LV Flash has an endurance of 1000 erase and write cycles and a ten year data retention capability. 11.3.1 Flash Programming and Security All Flash programming is performed by code in the SROM. The registers that control Flash programming are only visible to the M8C CPU when it is executing out of SROM. This makes it impossible to read, write, or erase the Flash by avoiding the security mechanisms implemented in the SROM. Customer firmware only programs Flash via SROM calls. The data or code images are sourced through any interface with the appropriate support firmware. This type of programming requires a `boot-loader'--a piece of firmware resident on the Flash. For safety reasons this boot-loader is not overwritten during firmware rewrites. The Flash provides four extra auxiliary rows to hold Flash block protection flags, boot time calibration values, configuration tables, and any device values. The routines to access these auxiliary rows are documented in the SROM section. The auxiliary rows are not affected by the device erase function. 11.3.2 In-System Programming enCoRe II LV devices enable in-system programming by using the P1.0 and P1.1 pins as the serial programming mode interface. This allows an external controller to make the enCoRe II LV part enter serial programming mode and then use the test queue to issue Flash access functions in the SROM. 11.4 SROM The SROM holds the code to boot the part, calibrate circuitry, and perform Flash operations (Table 11-1 lists the SROM functions). The functions of the SROM are accessed in normal user code or operating from Flash. The SROM exists in a separate memory space from user code. To access SROM functions, the Supervisory System Call instruction (SSC) is executed, which has an opcode of 00h. Before executing SSC, the M8C's accumulator is loaded with the desired SROM function code from Table 11-1. Undefined functions causes a HALT if called from user code. The SROM functions execute code with calls; therefore, the functions require stack space. With the exception of Reset, all of the SROM functions have a parameter block in SRAM that must be configured before executing the SSC. Table 11-2 lists all possible parameter block variables. The meaning of each parameter, with regards to a specific SROM function, is described later in this section. Table 11-1. SROM Function Codes Function Code 00h 01h 02h 03h 05h 06h 07h Function Name SWBootReset ReadBlock WriteBlock EraseBlock EraseAll TableRead CheckSum Stack Space 0 7 10 9 11 3 3 Document 38-16016 Rev. *E Page 15 of 68 [+] Feedback CY7C601xx, CY7C602xx Two important variables used for all functions are KEY1 and KEY2. These variables help discriminate between valid and inadvertent SSCs. KEY1 always has a value of 3Ah, while KEY2 has the same value as the stack pointer when the SROM function begins execution. This is the Stack Pointer value when the SSC opcode is executed, plus three. If either of the keys do not match the expected values, the M8C halts (with the exception of the SWBootReset function). The following code puts the correct value in KEY1 and KEY2. The code starts with a halt, to force the program to jump directly into the setup code and not run into it. halt SSCOP: mov [KEY1], 3ah mov X, SP mov A, X add A, 3 mov [KEY2], A Read, write, and erase operations may fail if the target block is read or write protected. Block protection levels are set during device programming. The EraseAll function overwrites data in addition to leaving the entire user Flash in the erase state. The EraseAll function loops through the number of Flash macros in the product, executing the following sequence: erase, bulk program all zeros, erase. After the user space in all Flash macros are erased, a second loop erases and then programs each protection block with zeros. 11.5 SROM Function Descriptions 11.5.1 SWBootReset Function The SROM function, SWBootReset, is responsible for transitioning the device from a reset state to running user code. The SWBootReset function is executed whenever the SROM is entered with an M8C accumulator value of 00h: the SRAM parameter block is not used as an input to the function. This happens, by design, after a hardware reset, because the M8C's accumulator is reset to 00h or when user code executes the SSC instruction with an accumulator value of 00h. The SWBootReset function does not execute when the SSC instruction is executed with a bad key value and a non zero function code. An enCoRe II LV device executes the HALT instruction if a bad value is given for either KEY1 or KEY2. The SWBootReset function verifies the integrity of the calibration data by way of a 16-bit checksum, before releasing the M8C to run user code. 11.5.2 ReadBlock Function The ReadBlock function is used to read 64 contiguous bytes from Flash: a block. The function first checks the protection bits and determines if the desired BLOCKID is readable. If read protection is turned on, the ReadBlock function exits setting the accumulator and KEY2 back to 00h. KEY1 has a value of 01h, indicating a read failure. If read protection is not enabled, the function reads 64 bytes from the Flash using a ROMX instruction and stores the results in SRAM using an MVI instruction. The first of the 64 bytes is stored in SRAM at the address indicated by the value of the POINTER parameter. When the ReadBlock completes successfully the accumulator, KEY1 and KEY2 all have a value of 00h. Table 11-4. ReadBlock Parameters Name KEY1 KEY2 BLOCKID POINTER Address 0,F8h 0,F9h 0,FAh 0,FBh 3Ah Stack Pointer value, when SSC is executed Flash block number First of 64 addresses in SRAM where returned data is stored Description Table 11-2. SROM Function Parameters Variable Name Key1/Counter/Return Code Key2/TMP BlockID Pointer Clock Mode Delay PCL 11.4.1 Return Codes The SROM also features Return Codes and Lockouts. Return codes determine the success or failure of a particular function. The return code is stored in KEY1's position in the parameter block. The CheckSum and TableRead functions do not have return codes because KEY1's position in the parameter block is used to return other data. Table 11-3. SROM Return Codes Return Code 00h 01h 02h 03h Success Function not allowed due to level of protection on block Software reset without hardware reset Fatal error, SROM halted Description SRAM Address 0,F8h 0,F9h 0,FAh 0,FBh 0,FCh 0,FDh 0,FEh 0,FFh Document 38-16016 Rev. *E Page 16 of 68 [+] Feedback CY7C601xx, CY7C602xx 11.5.3 WriteBlock Function The WriteBlock function is used to store data in Flash. Data is moved 64 bytes at a time from SRAM to Flash using this function. The WriteBlock function first checks the protection bits and determines if the desired BLOCKID is writable. If write protection is turned on, the WriteBlock function exits setting the accumulator and KEY2 back to 00h. KEY1 has a value of 01h, indicating a write failure. The configuration of the WriteBlock function is straightforward. The BLOCKID of the Flash block, where the data is stored, is determined and stored at SRAM address FAh. The SRAM address of the first of the 64 bytes to be stored in Flash is indicated using the POINTER variable in the parameter block (SRAM address FBh). Finally, the CLOCK and DELAY value are set correctly. The CLOCK value determines the length of the write pulse used to store the data in Flash. The CLOCK and DELAY values are dependent on the CPU speed and must be set correctly. Refer to the Clocking section for additional information. Table 11-5. WriteBlock Parameters Name KEY1 KEY2 BLOCK ID Address 0,F8h 0,F9h 0,FAh 3Ah Stack Pointer value, when SSC is executing 8 KB Flash block number (00h-7Fh) 4 KB Flash block number (00h-3Fh) 3 KB Flash block number (00h-2Fh) First 64 addresses in SRAM where the data is stored in Flash is located before calling WriteBlock Clock Divider used to set the write pulse width For a CPU speed of 12 MHz set to 56h Description Table 11-6. EraseBlock Parameters Name KEY1 KEY2 BLOCKID CLOCK DELAY Address 0,F8h 0,F9h 0,FAh 0,FCh 0,FEh 3Ah Stack Pointer value, when SSC is executed Flash block number (00h-7Fh) Clock Divider used to set the erase pulse width For a CPU speed of 12 MHz set to 56h Description 11.5.5 ProtectBlock Function The enCoRe II LV devices offer Flash protection on a block-by-block basis. Table 11-7 lists the protection modes available. In the table, ER and EW indicate the ability to perform external reads and writes; IW is used for internal writes. Internal reading is always permitted using the ROMX instruction. The ability to read using the SROM ReadBlock function is indicated by SR. The protection level is stored in two bits according to Table 11-7. These bits are bit packed into 64 bytes of the protection block. Therefore, each protection block byte stores the protection level for four Flash blocks. The bits are packed into a byte, with the lowest numbered block's protection level stored in the lowest numbered bits in Table 11-7. The first address of the protection block contains the protection level for blocks 0 through 3; the second address is for blocks 4 through 7. The 64th byte stores the protection level for blocks 252 through 255. Table 11-7. Protection Modes Mode 00b 01b 10b 11b Settings Description Marketing Unprotected Factory upgrade SR ER EW IW Unprotected SR ER EW IW Read protect POINTER 0,FBh CLOCK DELAY 0,FCh 0,FEh 11.5.4 EraseBlock Function The EraseBlock function is used to erase a block of 64 contiguous bytes in Flash. The EraseBlock function first checks the protection bits and determines if the desired BLOCKID is writable. If write protection is turned on, the EraseBlock function exits setting the accumulator and KEY2 back to 00h. KEY1 has a value of 01h, indicating a write failure. The EraseBlock function is only useful as the first step in programming. Erasing a block does not make data in a block fully unreadable. If the objective is to obliterate data in a block, the best method is to perform an EraseBlock followed by a WriteBlock of all zeros. To set up the parameter block for EraseBlock, correct key values must be stored in KEY1 and KEY2. The block number to be erased is stored in the BLOCKID variable and the CLOCK and DELAY values are set based on the current CPU speed. SR ER EW IW Disable external Field upgrade write SR ER EW IW Disable internal write 6 5 4 3 2 Full protection 7 1 0 Block n+3 Block n+2 Block n+1 Block n Only an EraseAll decreases the protection level by placing zeros in all locations of the protection block. To set the level of protection, the ProtectBlock function is used. This function takes data from SRAM, starting at address 80h, and ORs it with the current values in the protection block. The result of the OR operation is then stored in the protection block. The EraseBlock function does not change the protection level for a block. Because the SRAM location for the protection data is fixed and there is only one protection block per Flash macro, the ProtectBlock function expects very few variables in the parameter block to be set before calling the function. The parameter block values that are, besides the keys, are the CLOCK and DELAY values. Document 38-16016 Rev. *E Page 17 of 68 [+] Feedback CY7C601xx, CY7C602xx Table 11-8. ProtectBlock Parameters Name KEY1 KEY2 CLOCK DELAY Address 0,F8h 0,F9h 0,FCh 0,FEh 3Ah Stack Pointer value when SSC is executed Clock Divider used to set the write pulse width For a CPU speed of 12 MHz set to 56h Description 11.5.7 TableRead Function The TableRead function gives the user access to part specific data stored in the Flash during manufacturing. It also returns a Revision ID for the die (not to be confused with the Silicon ID). Table 11-10. Table Read Parameters Name KEY1 KEY2 BLOCKID Address 0,F8h 0,F9h 0,FAh 3Ah Description Stack Pointer value when SSC is executed. Table number to read. 11.5.6 EraseAll Function The EraseAll function performs a series of steps that destroy the user data in the Flash macros and resets the protection block in each Flash macro to all zeros (the unprotected state). The EraseAll function does not affect the three hidden blocks above the protection block in each Flash macro. The first of these four hidden blocks is used to store the protection table for its eight Kbytes of user data. The EraseAll function begins by erasing the user space of the Flash macro with the highest address range. A bulk program of all zeros is then performed on the same Flash macro, to destroy all traces of previous contents. The bulk program is followed by a second erase that leaves the Flash macro ready for writing. The erase, program, erase sequence is then performed on the next lowest Flash macro in the address space if it exists. Following erase of the user space, the protection block for the Flash macro with the highest address range is erased. Following erase of the protection block, zeros are written into every bit of the protection table. The next lowest Flash macro in the address space then has its protection block erased and filled with zeros. The result of the EraseAll function is that all user data in Flash is destroyed and the Flash is left in an unprogrammed state, ready to accept one of the various write commands. The protection bits for all user data are also reset to the zero state. Besides the keys, the CLOCK and DELAY parameter block values are also set. Table 11-9. EraseAll Parameters Name KEY1 KEY2 CLOCK DELAY Address 0,F8h 0,F9h 0,FCh 0,FEh 3Ah Stack Pointer value when SSC is executed Clock Divider used to set the write pulse width For a CPU speed of 12 MHz set to 56h Description The table space for the enCoRe II LV is simply a 64 byte row broken up into eight tables of eight bytes. The tables are numbered zero through seven. All user and hidden blocks in the CY7C601xx/CY7C602xx parts consist of 64 bytes. An internal table (Table 0) holds the Silicon ID and returns the Revision ID. The Silicon ID is returned in SRAM, while the Revision and Family IDs are returned in the CPU_A and CPU_X registers. The Silicon ID is a value placed in the table by programming the Flash and is controlled by Cypress Semiconductor Product Engineering. The Revision ID is hard coded into the SROM and also redundantly placed in SROM Table 1. This is discussed in more detail later in this section. SROM Table 1 holds Family/Die ID and Revision ID values for the device and returns a one-byte internal revision counter. The internal revision counter starts with a value of zero and is incremented when one of the other revision numbers is not incremented. It is reset to zero when one of the other revision numbers is incremented. The internal revision count is returned in the CPU_A register. The CPU_X register is always set to FFh when Table 1 is read. The CPU_A and CPU_X registers always return a value of FFh when Tables 2-7 are read. The BLOCKID value, in the parameter block, indicates which table must be returned to the user. Only the three least significant bits of the BLOCKID parameter are used by TableRead function for enCoRe II LV devices. The upper five bits are ignored. When the function is called, it transfers bytes from the table to SRAM addresses F8h-FFh. The M8C's A and X registers are used by the TableRead function to return the die's Revision ID. The Revision ID is a 16-bit value hard coded into the SROM that uniquely identifies the die's design. The return values for corresponding Table calls are tabulated as shown in Table 11-11. Table 11-11. Return Values for Table Read Table Number 0 1 2-7 Revision ID 0xFF Return Value A Family ID 0xFF Internal Revision Counter 0xFF X Document 38-16016 Rev. *E Page 18 of 68 [+] Feedback CY7C601xx, CY7C602xx 11.6 SROM Table Read Description The Silicon IDs for enCoRe II LV devices are stored in SROM tables in the part, as shown in Figure 11-3. on page 20 The Silicon ID can be read out from the part using SROM Table reads. This is demonstrated in the following pseudo code. As mentioned in the section SROM on page 15, the SROM variables occupy address F8h through FFh in the SRAM. Each of the variables and their definition are given in the section SROM on page 15. AREA SSCParmBlkA(RAM,ABS) org F8h // Variables are defined starting at address F8h ; F8h supervisory key ; F8h result code ;F9h supervisory stack ptr key ; FAh block ID ; FBh pointer to data buffer ; FCh Clock ; FDh ClockW ClockE multiplier ; FEh flash macro sequence delay count 1 ; FFh temporary result code SSC_KEY1: SSC_RETURNCODE: blk 1 SSC_KEY2 : blk 1 SSC_BLOCKID: blk 1 SSC_POINTER: blk 1 SSC_CLOCK: blk 1 SSC_MODE: blk 1 SSC_DELAY: blk 1 SSC_WRITE_ResultCode: blk _main: mov mov A, 2 [SSC_BLOCKID], A// To read from Table 2 - trim values for the IMO are stored in table 2 mov mov add mov X, SP ; copy SP into X A, X ; A temp stored in X A, 3 ; create 3 byte stack frame (2 + pushed A) [SSC_KEY2], A ; save stack frame for supervisory code ; load the supervisory code for flash operations mov [SSC_KEY1], 3Ah ;FLASH_OPER_KEY - 3Ah mov Table 11-1 SSC ; SSC call the supervisory ROM A,6 ; load A with specific operation. 06h is the code for Table read // At the end of the SSC command the silicon ID is stored in F8 (MSB) and F9(LSB) of the SRAM .terminate: jmp .terminate Document 38-16016 Rev. *E Page 19 of 68 [+] Feedback CY7C601xx, CY7C602xx Figure 11-3. SROM Table F8h F9h FAh FBh FCh FDh FEh FFh Table 0 Silicon ID [15-8] Silicon ID [7-0] lid in g Va rat n pe i o O Re g Table 1 Family / Die ID Revision ID Table 2 24 MHz IOSCTR at 3.30V 32 KHz at 3.30V 32 KHz at 3.00V 32 KHz at 2.85V 32 KHz at 2.70V 24 MHz IOSCTR at 3.00V 24 MHz IOSCTR at 2.85V 24 MHz IOSCTR at 2.70V Table 3 LPOSCTR LPOSCTR LPOSCTR LPOSCTR Table 4 Table 5 Table 6 Table 7 11.6.1 Checksum Function The Checksum function calculates a 16-bit checksum over a user specifiable number of blocks, within a single Flash macro (Bank) starting from block zero. The BLOCKID parameter is used to pass in the number of blocks to calculate the checksum over. A BLOCKID value of `1' calculates the checksum of only block 0, while a BLOCKID value of `0' calculates the checksum of all 256 user blocks. The 16-bit checksum is returned in KEY1 and KEY2. The parameter KEY1 holds the lower eight bits of the checksum and the parameter KEY2 holds the upper eight bits of the checksum. The checksum algorithm executes the following sequence of three instructions over the number of blocks times 64 to be checksummed. romx add [KEY1], A adc [KEY2], 0 Table 11-12. Checksum Parameters Name KEY1 KEY2 BLOCKID Address 0,F8h 0,F9h 0,FAh 3Ah Stack Pointer value when SSC is executed Number of Flash blocks to calculate checksum on Description Document 38-16016 Rev. *E Page 20 of 68 [+] Feedback CY7C601xx, CY7C602xx 12. Clocking The enCoRe II LV has two internal oscillators, the internal 24 MHz oscillator and the 32 kHz low power oscillator. The internal 24 MHz oscillator is designed such that it is trimmed to an output frequency of 24 MHz over temperature and voltage variation. The internal 24 MHz oscillator accuracy is 24 MHz -22% to +10% (between 0 and 70C). No external components are required to achieve this level of accuracy. Firmware is responsible for selecting the correct trim values from the user row to match the power supply voltage in the end application and writing the values to the trim registers IOSCTR and LPOSCTR. The internal low speed oscillator of nominally 32 kHz provides a slow clock source for the enCoRe II LV in suspend mode, particularly to generate a periodic wakeup interrupt and also to provide a clock to sequential logic during power up and power down events when the main clock is stopped. In addition, this oscillator can be used as a clocking source for the Interval Timer clock (ITMRCLK) and Capture Timer clock (TCAPCLK). The 32 kHz low power oscillator can operate in low power mode or provide a more accurate clock in normal mode. The internal 32 kHz low power oscillator accuracy ranges from -53.12% to +56.25%. The 32 kHz low power oscillator can be calibrated against the internal 24 MHz oscillator or another timing source, if desired. enCoRe II LV provides the ability to load new trim values for the 24 MHz oscillator based on voltage. This allows Vdd to be monitored and have firmware trim the oscillator based on voltage present. The IOSCTR register is used to set trim values for the 24 MHz oscillator. enCoRe II LV is initialized with 3.30V trim values at power on, then firmware is responsible for transferring the correct set of trim values to the trim registers to match the application's actual Vdd. The 32 kHz oscillator generally does not require trim adjustments for voltage but trim values for the 32 kHz are also stored in Supervisory ROM. To improve the accuracy of the IMO, new trim values are loaded based on supply voltage to the part. For this, firmware needs to make modifications to two registers: 1. The internal oscillator trim register at location 0x34. 2. The gain register at location 0x38. 12.1 Trim Values for the IOSCTR Register The trim values are stored in SROM tables in the part as shown in Figure 11-3. The trim values are read out from the part based on voltage settings and written to the IOSCTR register at location 0x34. The following pseudo code shows how this is done. _main: mov A, 2 mov [SSC_BLOCKID], A Call SROM operation to read the SROM table (Refer to section SROM Table Read Description on page 19) //After this command is executed, the trim //values for 3.3, 3.0, 2.85 and 2.7 are stored //at locations FC through FF in the RAM. SROM //calls are explained in the previous section of //this data sheet ; mov A, [FCh] // trim values for 3.3V mov A, [FDh] // trim values for 3.0V ; mov A, [FEh] // trim values for 2.85V ; mov A, [FFh] // trim values for 2.70V mov reg[IOSCTR],A // Loading IOSCTR with // trim values for // 3.0V .terminate: jmp .terminate Gain value for the register at location [0x38]: 3.3V = 0x40 3.0V = 0x40 2.85V = 0xFF 2.70V = 0xFF Load register [0x38] with the gain values corresponding to the appropriate voltage. Table 12-1. Oscillator Trim Values vs. Voltage Settings Supervisory ROM Table Table2 FCh Table2 FDh Table2 FEh Table2 FFh Table3 F8h Table3 F9h Function 24 MHz IOSCTR at 3.30V 24 MHz IOSCTR at 3.00V 24 MHz IOSCTR at 2.85V 24 MHz IOSCTR at 2.70V 32 kHz LPOSCTR at 3.30V 32 kHz LPOSCTR at 3.00V Document 38-16016 Rev. *E Page 21 of 68 [+] Feedback CY7C601xx, CY7C602xx When using the 32 kHz oscillator, the PITMRL/H is read until two consecutive readings match before sending and receiving data. The following firmware example assumes the developer is interested in the lower byte of the PIT. Read_PIT_counter: mov A, reg[PITMRL] mov [57h], A mov A, reg[PITMRL] mov [58h],A mov [59h], A mov A, reg[PITMRL] mov [60h], A ;;;Start comparison mov A,[60h] mov X, [59h] sub A, [59h] jz done mov A, [59h] mov X, [58h] sub A, [58h] jz done mov X, [57h] ;;;correct data is in memory location 57h done: mov [57h], X ret The CY7C601xx part is optionally sourced from an external crystal oscillator. The external clock driving on CLKIN range is from 187 KHz to 24 MHz. 12.2 Clock Architecture Description The enCoRe II LV clock selection circuitry allows the selection of independent clocks for the CPU, Interval Timers, and Capture Timers. On the CY7C601xx, the external oscillator is sourced by the crystal oscillator. When the crystal oscillator is disabled, it is sourced directly from the CLKIN pin. The external crystal oscillator is fed through the EFTB block, which is optionally bypassed. 12.2.1 CPU Clock The CPU clock, CPUCLK, is sourced from the external crystal oscillator, the internal 24 MHz oscillator, or the Internal 32 kHz low power oscillator. The selected clock source can optionally be divided by 2n-1 where n is 0-7 (see Table 12-3). When it is not being used by the external crystal oscillator, the CLKOUT pin is driven from one of many sources. This is used for test and also in some applications. The sources that drive the CLKOUT are: CLKIN after the optional EFTB filter. Internal 24 MHz Oscillator. Internal 32 kHz Oscillator. CPUCLK after the programmable divider. Document 38-16016 Rev. *E Page 22 of 68 [+] Feedback CY7C601xx, CY7C602xx Figure 12-1. CPU Clock Block Diagram EN XOSC SEL P0.1 CLKOUT XTAL OSC 1-24MHz P0.0 CLKIN CY7C601xx only Crystal Oscillator Disabled MUX CY7C601xx only EFTB CLK_EXT LP OSC 32-KHz CLK_32KHz CPUCLK SEL CLK_EXT MUX SCALE (divide by 2n, n = 0-5,7) CLK_CPU CLK_24MHz Doubler CLK_HS Table 12-2. CPU Clock Configuration (CPUCLKCR) [0x30] [R/W] Bit # Field Read/Write Default - 0 - 0 - 0 7 6 5 4 Reserved - 0 - 0 - 0 - 0 3 2 1 0 CPUCLK Select R/W 0 Bit [7:1]: Reserved Bit 0: CPU CLK Select 0 = Internal 24 MHz Oscillator 1 = External oscillator source Note The CPU speed selection is configured using the OSC_CR0 Register (Table 12-3). Table 12-3. OSC Control 0 (OSC_CR0) [0x1E0] [R/W] Bit # Field 7 Reserved 6 5 No Buzz 4 3 2 1 CPU Speed [2:0] 0 Sleep Timer [1:0] Document 38-16016 Rev. *E Page 23 of 68 [+] Feedback CY7C601xx, CY7C602xx Table 12-3. OSC Control 0 (OSC_CR0) [0x1E0] [R/W] (continued) Read/Write Default - 0 - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit [7:6]: Reserved Bit 5: No Buzz During sleep (the Sleep bit is set in the CPU_SCR Register--Table 13-1), the LVD and POR detection circuit is turned on periodically to detect any POR and LVD events on the VCC pin (the Sleep Duty Cycle bits in the ECO_TR are used to control the duty cycle--Table 15-3). To facilitate the detection of POR and LVD events, the No Buzz bit is used to continuously enable the LVD and POR detection circuit during sleep. This results in a faster response to an LVD or POR event during sleep at the expense of a slightly higher than average sleep current. Obtaining the absolute lowest power usage in sleep mode requires the No Buzz bit be clear. 0 = The LVD and POR detection circuit is turned on periodically as configured in the Sleep Duty Cycle. 1 = The Sleep Duty Cycle value is overridden. The LVD and POR detection circuit is always enabled. Note The periodic Sleep Duty Cycle enabling is independent with the sleep interval shown in the Sleep [1:0] bits below. Bit [4:3]: Sleep Timer [1:0] Sleep Timer [1:0] 00 01 10 11 Sleep Timer Clock Frequency (Nominal) 512 Hz 64 Hz 8 Hz 1 Hz Sleep Period (Nominal) 1.95 ms 15.6 ms 125 ms 1 sec Watchdog Period (Nominal) 6 ms 47 ms 375 ms 3 sec Note Sleep intervals are approximate. Bit [2:0]: CPU Speed [2:0] The enCoRe II LV operates over a range of CPU clock speeds. The reset value for the CPU Speed bits is zero; therefore, the default CPU speed is 3 MHz. CPU Speed [2:0] 000 001 010 011 100 101 110 111 CPU when Internal Oscillator is selected 3 MHz (Default) 6 MHz 12 MHz Reserved 1.5 MHz 750 KHz 187 KHz Reserved External Clock Clock In/8 Clock In/4 Clock In/2 Reserved Clock In/16 Clock In/32 Clock In/128 Reserved Note This register exists in the second bank of IO space. This requires setting the XIO bit in the CPU flags register. Document 38-16016 Rev. *E Page 24 of 68 [+] Feedback CY7C601xx, CY7C602xx Table 12-4. Clock IO Configuration (CLKIOCR) [0x32] [R/W] Bit # Field Read/Write Default - 0 7 6 Reserved - 0 - 0 5 4 XOSC Select R/W 0 3 XOSC Enable R/W 0 2 EFTB Disabled R/W 0 1 CLKOUT Select R/W 0 R/W 0 0 Bit [7:5]: Reserved Bit 4: XOSC Select This bit, when set, selects the external crystal oscillator clock as clock source of external clock. When selecting the crystal oscillator clock, first enable the crystal oscillator and wait for few cycles. This is the oscillator stabilization period. Then select the crystal clock as clock source. Similarly, to deselect crystal clock, first deselect crystal clock as clock source then disable the crystal oscillator. 0 = Not select external crystal oscillator clock. 1 = Select the external crystal oscillator clock. Bit 3: XOSC Enable This bit is only available on the CY7C601xx. This bit when set enables the external crystal oscillator. The external crystal oscillator shares pads CLKIN and CLKOUT with two GPIOs--P0.0 and P0.1 respectively. When the external crystal oscillator is enabled, the CLKIN signal comes from the external crystal oscillator block and the output enables on the GPIOs for P0.0 and P0.1 are disabled, eliminating the possibility of contention. When the external crystal oscillator is disabled, the source for CLKIN signal comes from the P0.0 GPIO input. 0 = Disable the external oscillator. 1 = Enable the external oscillator. Note The external crystal oscillator startup time takes up to 2 ms. Bit 2: EFTB Disabled This bit is only available on the CY7C601xx. 0 = Enable the EFTB filter. 1 = Disable the EFTB filter, causing CLKIN to bypass the EFTB filter. Bit [1:0]: CLKOUT Select 0 0 = Internal 24 MHz Oscillator 0 1 = External oscillator source 1 0 = Internal 32 kHz low power oscillator 1 1 = CPUCLK 12.2.2 Interval Timer Clock (ITMRCLK) The Interval Timer Clock (ITMRCLK) is sourced from the external crystal oscillator, the internal 24 MHz oscillator, the internal 32 kHz low power oscillator, or the Timer Capture clock. A programmable prescaler of 1, 2, 3, or 4 then divides the selected source. The 12-bit Programmable Interval Timer is a simple down counter with a programmable reload value. It provides a 1 s resolution by default. When the down counter reaches zero, the next clock is spent reloading. The reload value is read and written when the counter is running, but ensure that the counter does not unintentionally reload when the 12-bit reload value is only partially stored--between two writes of the 12-bit value. The programmable interval timer generates an interrupt to the CPU on each reload. The parameters to be set shows up on the device editor view of PSoC Designer when you place the enCoRe II LV timer user module. The parameters are PITIMER_Source and PITIMER_Divider. The PITIMER_Source is the clock to the timer and the PITIMER_Divider is the value the clock is divided by. The interval register (PITMR) holds the value that is loaded into the PIT counter on terminal count. The programmable interval timer resolution is configurable. For example: TCAPCLK divide by x of CPU clock (for example TCAPCLK divide by 2 of a 24 MHz CPU clock gives a frequency of 12 MHz) ITMRCLK divide by x of TCAPCLK (for example, ITMRCLK divide by 3 of TCAPCLK is 4 MHz so resolution is 0.25 s) Document 38-16016 Rev. *E Page 25 of 68 [+] Feedback CY7C601xx, CY7C602xx Figure 12-2. Programmable Interval Timer Block Diagram Configuration Status and Control 12-bit reload value System Clock Clock Timer 12-bit down counter 12-bit reload control Interrupt Controller 12.2.3 Timer Capture Clock (TCAPCLK) The Timer Capture clock (TCAPCLK) is sourced from the external crystal oscillator, the internal 24 MHz oscillator or the internal 32 kHz low power oscillator. A programmable prescaler of 2, 4, 6, or 8 then divides the selected source. Figure 12-3. Timer Capture Block Diagram System Clock Configuration Status and Control Captimer Clock 16-bit counter Prescale Mux Capture Registers 1ms timer Overflow Interrupt Capture0 Int Capture1 Int Interrupt Controller Document 38-16016 Rev. *E Page 26 of 68 [+] Feedback CY7C601xx, CY7C602xx Table 12-5. Timer Clock Configuration (TMRCLKCR) [0x31] [R/W] Bit # Field Read/Write Default 7 6 5 4 3 2 1 ITMRCLK Select R/W 1 R/W 1 0 TCAPCLK Divider R/W 1 R/W 0 TCAPCLK Select R/W 0 R/W 0 ITMRCLK Divider R/W 1 R/W 1 Bit [7:6]: TCAPCLK Divider [1:0] TCAPCLK Divider controls the TCAPCLK divisor. 0 0 = Divider Value 2 0 1 = Divider Value 4 1 0 = Divider Value 6 1 1 = Divider Value 8 Bit [5:4]: TCAPCLK Select The TCAPCLK Select field controls the source of the TCAPCLK. 0 0 = Internal 24 MHz Oscillator 0 1 = External Crystal Oscillator--external crystal oscillator on CLKIN and CLKOUT if the external crystal oscillator is enabled, CLKIN input if the external crystal oscillator is disabled (the XOSC Enable bit of the CLKIOCR Register is cleared--Table 12-4.) 1 0 = Internal 32 kHz Oscillator 1 1 = TCAPCLK Disabled Note The 1024 s interval timer is based on the assumption that TCAPCLK is running at 4 MHz. Changes in TCAPCLK frequency cause a corresponding change in the 1024 s interval timer frequency. Bit [3:2]: ITMRCLK Divider ITMRCLK Divider controls the ITMRCLK divisor. 0 0 = Divider value of 1 0 1 = Divider value of 2 1 0 = Divider value of 3 1 1 = Divider value of 4 Bit [1:0]: ITMRCLK Select 0 0 = Internal 24 MHz Oscillator 0 1 = External crystal oscillator--external crystal oscillator on CLKIN and CLKOUT if the external crystal oscillator is enabled, CLKIN input if the external crystal oscillator is disabled. 1 0 = Internal 32 kHz Oscillator 1 1 = TCAPCLK Note Changing the source of TMRCLK requires both the source and destination clocks to be running. It is not possible to change the clock source away from TCAPCLK after that clock is stopped. Document 38-16016 Rev. *E Page 27 of 68 [+] Feedback CY7C601xx, CY7C602xx 12.2.4 Internal Clock Trim Table 12-6. IOSC Trim (IOSCTR) [0x34] [R/W] Bit # Field Read/Write Default R/W 0 7 6 foffset[2:0] R/W 0 R/W 0 R/W D R/W D 5 4 3 2 Gain[4:0] R/W D R/W D R/W D 1 0 The IOSC Calibrate Register is used to calibrate the internal oscillator. The reset value is undefined, but during boot the SROM writes a calibration value that is determined during manufacturing test. The `D' indicates that the default value is trimmed to 24 MHz at 3.30V at power on. Bit [7:5]: foffset [2:0] This value is used to trim the frequency of the internal oscillator. These bits are not used in factory calibration and is zero. Setting each of these bits causes the appropriate fine offset in oscillator frequency. foffset bit 0 = 7.5 kHz foffset bit 1 = 15 kHz foffset bit 2 = 30 kHz Bit [4:0]: Gain [4:0] The effective frequency change of the offset input is controlled through the gain input. A lower value of the gain setting increases the gain of the offset input. This value sets the size of each offset step for the internal oscillator. Nominal gain change (KHz/offsetStep) at each bit, typical conditions (24 MHz operation): Gain bit 0 = -1.5 kHz Gain bit 1 = -3.0 kHz Gain bit 2 = -6 kHz Gain bit 3 = -12 kHz Gain bit 4 = -24 kHz 12.2.5 External Clock Trim Table 12-7. XOSC Trim (XOSCTR) [0x35] [R/W] Bit # Field Read/Write Default - 0 7 6 Reserved - 0 - 0 R/W D 5 4 3 XOSC XGM [2:0] R/W D R/W D 2 1 Reserved - - 0 Mode R/W D This register is used to calibrate the external crystal oscillator. The reset value is undefined, but during boot the SROM writes a calibration value that is determined during manufacturing test. This is the meaning of `D' in the Default field. Bit [7:5]: Reserved Bit [4:2]: XOSC XGM [2:0] Amplifier transconductance setting. The Xgm settings are recommended for resonators with frequencies of interest for the enCoRe II LV as below: Resonator 6 MHz Crystal 12 MHz Crystal Reserved 6 MHz Ceramic 12 MHz Ceramic XGM Setting 001 011 111 001 011 Worst Case R (Ohms) 403 201 70.4 41 Bit 1: Reserved Bit 0: Mode 0 = Oscillator Mode 1 = Fixed Maximum Bias Test Mode Document 38-16016 Rev. *E Page 28 of 68 [+] Feedback CY7C601xx, CY7C602xx 12.2.6 LPOSC Trim Table 12-8. LPOSC Trim (LPOSCTR) [0x36] [R/W] Bit # Field Read/Write Default 7 32 kHz Low Power R/W 0 6 Reserved - - 5 4 3 2 1 0 32 kHz Bias Trim [1:0] R/W D R/W D R/W D 32 kHz Freq Trim [3:0] R/W D R/W D R/W D This register is used to calibrate the 32 kHz low speed oscillator. The reset value is undefined but during boot the SROM writes a calibration value that is determined during manufacturing test. This is the meaning of `D' in the Default field. The trim value is adjusted vs. voltage as noted in Table 12-2. Bit 7: 32 kHz Low Power 0 = The 32 kHz low speed oscillator operates in normal mode. 1 = The 32 kHz low speed oscillator operates in a low power mode. The oscillator continues to function normally but with reduced accuracy. Bit 6: Reserved Bit [5:4]: 32 kHz Bias Trim [1:0] These bits control the bias current of the low power oscillator. 0 0 = Mid bias 0 1 = High bias 1 0 = Reserved 1 1 = Reserved Note Do not program the 32 kHz Bias Trim [1:0] field with the reserved 10b value as the oscillator does not oscillate at all corner conditions with this setting. Bit [3:0]: 32 kHz Freq Trim [3:0] These bits are used to trim the frequency of the low power oscillator. 12.3 CPU Clock During Sleep Mode When the CPU enters sleep mode the CPUCLK Select (Bit 0, Table 12-2) is forced to the internal oscillator, and the oscillator is stopped. When the CPU comes out of sleep mode it runs on the internal oscillator. The internal oscillator recovery time is three clock cycles of the internal 32 kHz low power oscillator. If the system requires the CPU to run off the external clock after waking from sleep mode, firmware needs to switch the clock source for the CPU. If the external clock source is the external oscillator and the oscillator is disabled, firmware needs to enable the external oscillator, wait for it to stabilize, and then change the clock source. Document 38-16016 Rev. *E Page 29 of 68 [+] Feedback CY7C601xx, CY7C602xx 13. Reset The microcontroller supports two types of resets: Power on Reset (POR) and Watchdog Reset (WDR). When reset is initiated, all registers are restored to their default states and all interrupts are disabled. The occurrence of a reset is recorded in the System Status and Control Register (CPU_SCR). Bits within this register record the occurrence of POR and WDR Reset respectively. The firmware interrogates these bits to determine the cause of a reset. The microcontroller resumes execution from Flash address 0x0000 after a reset. The internal clocking mode is active after a reset, until changed by user firmware. Note The CPU clock defaults to 3 MHz (internal 24 MHz oscillator divide-by-8 mode) at POR to guarantee operation at the low VCC that might be present during the supply ramp. Table 13-1. System Status and Control Register (CPU_SCR) [0xFF] [R/W] Bit # Field Read/Write Default 7 GIES R 0 6 Reserved - 0 5 WDRS R/C[3] 0 4 PORS R/C[3] 1 3 Sleep R/W 0 2 Reserved - 1 1 Reserved - 0 0 Stop R/W 0 The bits of the CPU_SCR register are used to convey status and control of events for various functions of an enCoRe II LV device. Bit 7: GIES The Global Interrupt Enable Status bit is a read only status bit and its use is discouraged. The GIES bit is a legacy bit, which was used to provide the ability to read the GIE bit of the CPU_F register. However, the CPU_F register is now readable. When this bit is set, it indicates that the GIE bit in the CPU_F register is also set which, in turn, indicates that the microprocessor services interrupts. 0 = Global interrupts disabled 1 = Global interrupt enabled Bit 6: Reserved Bit 5: WDRS The WDRS bit is set by the CPU to indicate that a WDR event has occurred. The user can read this bit to determine the type of reset that has occurred. The user can clear but not set this bit. 0 = No WDR 1 = A WDR event has occurred Bit 4: PORS The PORS bit is set by the CPU to indicate that a POR event has occurred. The user can read this bit to determine the type of reset that has occurred. The user can clear but not set this bit. 0 = No POR 1 = A POR event has occurred. (Note that WDR events does not occur until this bit is cleared.) Bit 3: SLEEP Set by the user to enable CPU sleep state. CPU remains in sleep mode until any interrupt is pending. The Sleep bit is covered in more detail in the Sleep Mode section. 0 = Normal operation 1 = Sleep Bit [2:1]: Reserved Bit 0: STOP This bit is set by the user to halt the CPU. The CPU remains halted until a reset (WDR, POR, or external reset) takes place. If an application wants to stop code execution until a reset, the preferred method is to use the HALT instruction rather than writing to this bit. 0 = Normal CPU operation 1 = CPU is halted (not recommended) Document 38-16016 Rev. *E Page 30 of 68 [+] Feedback CY7C601xx, CY7C602xx 13.1 Power On Reset POR occurs every time the power to the device is switched on. POR is released when the supply is typically 2.6V for the upward supply transition, with typically 50 mV of hysteresis during the power on transient. Bit 4 of the System Status and Control Register (CPU_SCR) is set to record this event (the register contents are set to 00010000 by the POR). After a POR, the microprocessor is held off for approximately 20 ms for the VCC supply to stabilize before executing the first instruction at address 0x00 in Flash. If the VCC voltage drops below the POR downward supply trip point, POR is reasserted. The VCC supply needs to ramp linearly from 0 to VCC in less than 200 ms. Note The PORS status bit is set at POR and is only cleared by the user; it cannot be set by firmware. WDT cannot be disabled. The only exception to this is if a POR event takes place, which disables the WDT. The sleep timer is used to generate the sleep time period and the watchdog time period. The sleep timer uses the internal 32 kHz low power oscillator system clock to produce the sleep time period. The user programs the sleep time period using the sleep timer bits of the OSC_CR0 Register (Table 12-3). When the sleep time elapses (sleep timer overflows), an interrupt to the sleep timer Interrupt Vector is generated. The watchdog timer period is automatically set to be three counts of the sleep timer overflow. This represents between two and three sleep intervals depending on the count in the sleep timer at the previous WDT clear. When this timer reaches three, a WDR is generated. The user either clears the WDT, or the WDT and the sleep timer. Whenever the user writes to the Reset WDT Register (RES_WDT), the WDT is cleared. If the data written is the hex value 0x38, the sleep timer is also cleared at the same time. 13.2 Watchdog Timer Reset The user has the option to enable the WDT. The WDT is enabled by clearing the PORS bit. When the PORS bit is cleared, the Table 13-2. Reset Watchdog Timer (RESWDT) [0xE3] [W] Bit # Field Read/Write Default W 0 W 0 W 0 7 6 5 4 3 2 1 0 Reset Watchdog Timer [7:0] W 0 W 0 W 0 W 0 W 0 Any write to this register clears the watchdog timer, a write of 0x38 also clears the sleep timer. Bit [7:0]: Reset Watchdog Timer [7:0] 14. Sleep Mode The CPU is put to sleep only by the firmware. This is accomplished by setting the Sleep bit in the System Status and Control Register (CPU_SCR). This stops the CPU from executing instructions, and the CPU remains asleep until an interrupt is pending, or there is a reset event (either a Power on Reset or a Watchdog Timer Reset). The Low Voltage Detection circuit (LVD) drops into fully functional power reduced states, and the latency for the LVD is increased. The actual latency is traded against power consumption by changing Sleep Duty Cycle field of the ECO_TR Register. The internal 32 kHz low speed oscillator remains running. Before entering suspend mode, firmware optionally configures the 32 kHz low speed oscillator to operate in a low power mode to help reduce the overall power consumption (using the 32 kHz low power bit, Table 12-8). This helps to save approximately 5 A; however, the trade off is that the 32 kHz low speed oscillator is less accurate (-53.12% to +56.25% deviation). All interrupts remain active. Only the occurrence of an interrupt wakes the part from sleep. The Stop bit in the System Status and Control Register (CPU_SCR) is cleared for a part to resume out of sleep. The Global Interrupt Enable bit of the CPU Flags Register (CPU_F) does not have any effect. Any unmasked interrupt wakes the system. As a result, any interrupt not intended for waking is disabled through the Interrupt Mask Registers. When the CPU enters sleep mode the CPUCLK Select (Bit 1, Table 12-2) is forced to the internal oscillator. The internal oscillator recovery time is three clock cycles of the internal 32 kHz low power oscillator. The internal 24 MHz oscillator restarts immediately on exiting sleep mode. If the external crystal oscillator is used, firmware needs to switch the clock source for the CPU. Unlike the internal 24 MHz oscillator, the external oscillator is not automatically shut down during sleep. Systems that need the external oscillator disabled in sleep mode needs to disable the external oscillator before entering sleep mode. In systems where the CPU runs off the external oscillator, firmware needs to switch the CPU to the internal oscillator before disabling the external oscillator. On exiting sleep mode, after the clock is stable and the delay time has expired, the instruction immediately following the sleep instruction is executed before the interrupt service routine (if enabled). The sleep interrupt allows the microcontroller to wake up periodically and poll system components while maintaining very low average power consumption. The sleep interrupt is also used to provide periodic interrupts during non-sleep modes. Note 3. C = Clear. This bit can only be cleared by the user and cannot be set by firmware. Document 38-16016 Rev. *E Page 31 of 68 [+] Feedback CY7C601xx, CY7C602xx 14.1 Sleep Sequence The SLEEP bit is an input into the sleep logic circuit. This circuit is designed to sequence the device into and out of the hardware sleep state. The hardware sequence to put the device to sleep is shown in Figure 14-1. and is defined as follows. 1. Firmware sets the SLEEP bit in the CPU_SCR0 register. The Bus Request (BRQ) signal to the CPU is immediately asserted. This is a request by the system to halt CPU operation at an instruction boundary. The CPU samples BRQ on the positive edge of CPUCLK. 2. Due to the specific timing of the register write, the CPU issues a Bus Request Acknowledge (BRA) on the following positive edge of the CPU clock. The sleep logic waits for the following negative edge of the CPU clock and then asserts a system wide Power Down (PD) signal. In Figure 14-1. the CPU is halted and the system wide power down signal is asserted. 3. The system wide PD signal controls several major circuit blocks: the Flash memory module, the internal 24 MHz oscillator, the EFTB filter, and the bandgap voltage reference. These circuits transition into a zero power state. The only operational circuits on chip are the low power oscillator, the bandgap refresh circuit, and the supply voltage monitor (POR/LVD) circuit. The external crystal oscillator on enCoRe II LV devices is not automatically powered down when the CPU enters the sleep state. Firmware must explicitly disable the external crystal oscillator to reduce power to levels specified. 14.1.1 Low Power in Sleep Mode To achieve the lowest possible power consumption during suspend or sleep, the following conditions are observed in addition to considerations for the sleep timer and external crystal oscillator: All GPIOs are set to outputs and driven low Clear P11CR[0], P10CR[0] Set P10CR[1] Make sure 32 KHz oscillator clock is not selected as clock source to ITMRCLK, TCAPCLK, and not even as clock output source onto P01_CLKOUT pin. All the other blocks go to the power down mode automatically on suspend. The following steps are user configurable and help in reducing the average suspend mode power consumption. 1. Configure the power supply monitor at a large regular intervals, control register bits are 1,EB[7:6] (power system sleep duty cycle PSSDC[1:0]). 2. Configure the low power oscillator into low power mode, control register bit is LOPSCTR[7]. For low power considerations during sleep when external clock is used as the CPUCLK source, the clock source must be held low to avoid unintentional leakage current. If the clock is held high, then there may be a leakage through M8C. To avoid current consumption make sure ITMRCLK and TCPCLK are not sourced by either low power 32 KHz oscillator or 24 MHz crystal-less oscillator. Do not select 24 MHz or 32 KHz oscillator clocks on to the P01_CLKOUT pin. Figure 14-1. Sleep Timing Firmware write to SCR SLEEP bit causes an immediate BRQ CPU CPU captures BRQ on next CPUCLK responds with a BRA edge On the falling edge of CPUCLK, PD is asserted. The 24/48 MHz system clock is halted; the Flash and bandgap are powered down CPUCLK IOW SLEEP BRQ BRA PD Document 38-16016 Rev. *E Page 32 of 68 [+] Feedback CY7C601xx, CY7C602xx 14.2 Wakeup Sequence When asleep, the only event that wakes the system up is an interrupt. The global interrupt enable of the CPU flag register need not be set. Any unmasked interrupt wakes the system up. It is optional for the CPU to actually take the interrupt after the wakeup sequence. The wakeup sequence is synchronized to the 32 kHz clock for purposes of sequencing a startup delay, to allow the Flash memory module enough time to power up before the CPU asserts the first read access. Another reason for the delay is to allow the oscillator, Bandgap, and LVD and POR circuits time to settle before actually being used in the system. As shown in Figure 14-2., the wakeup sequence is as follows: 1. The wakeup interrupt occurs and is synchronized by the negative edge of the 32 kHz clock. 2. At the following positive edge of the 32 kHz clock, the system wide PD signal is negated. The Flash memory module, internal oscillator, EFTB, and bandgap circuit are all powered up to a normal operating state. 3. At the following positive edge of the 32 kHz clock, the current values for the precision POR and LVD have settled and are sampled. 4. At the following negative edge of the 32 kHz clock (after about 15 s nominal), the BRQ signal is negated by the sleep logic circuit. On the following CPUCLK, BRA is negated by the CPU and instruction execution resumes. Note that in Figure 14-2. fixed function blocks, such as Flash, internal oscillator, EFTB, and bandgap, have about 15 s start up. The wakeup times (interrupt to CPU operational) range from 75 s to 105 s. Figure 14-2. Wakeup Timing Interrupt is double sam pled by Sleep Tim er or G PIO 32K clock and PD is negated to interrupt occurs system C PU is restarted after 90m s (nom inal) C LK32K IN T SLEEP PD BANDGAP EN ABLE SAM PLE SAM PLE LVD / PO R C PU C LK/ 24M H z BR Q BR A C PU (N ot to S cale) Document 38-16016 Rev. *E Page 33 of 68 [+] Feedback CY7C601xx, CY7C602xx 15. Low Voltage Detect Control Table 15-1. Low Voltage Control Register (LVDCR) [0x1E3] [R/W] Bit # Field Read/Write Default - 0 7 Reserved - 0 R/W 0 6 5 PORLEV[1:0] R/W 0 4 3 Reserved - 0 R/W 0 2 1 VM[2:0] R/W 0 R/W 0 0 This register controls the configuration of the Power on Reset and Low Voltage Detection circuit. This register is accessed only in the second bank of IO space. This requires setting the XIO bit in the CPU flags register. Bit [7:6]: Reserved Bit [5:4]: PORLEV[1:0] This field controls the level below which the precision power on-reset (PPOR) detector generates a reset. 0 0 = 2.7V Range (trip near 2.6V) 0 1 = 3V Range (trip near 2.9V) 1 0 = Reserved 1 1 = PPOR does not generate a reset, but values read from the Voltage Monitor Comparators Register (Table 15-2) give the internal PPOR comparator state with trip point set to the 3V range setting. Bit 3: Reserved Bit [2:0]: VM[2:0] This field controls the level below which the low-voltage-detect trips--possibly generating an interrupt and the level at which Flash is enabled for operation. Note This register exists in the second bank of IO space. This requires setting the XIO bit in the CPU flags register. VM[2:0] 000 001 010 011 100 101 110 111 LVD Trip Point (V) Min 2.69 2.90 3.00 3.10 Max 2.72 2.94 3.04 3.15 Reserved Reserved Reserved Reserved Typical 2.7 2.92 3.02 3.13 Document 38-16016 Rev. *E Page 34 of 68 [+] Feedback CY7C601xx, CY7C602xx 15.1 POR Compare State Table 15-2. Voltage Monitor Comparators Register (VLTCMP) [0x1E4] [R] Bit # Field Read/Write Default - 0 - 0 - 0 7 6 5 Reserved - 0 - 0 - 0 4 3 2 1 LVD R 0 0 PPOR R 0 This read-only register allows reading the current state of the LVD and PPOR comparators. Bit [7:2]: Reserved Bit 1: LVD This bit is set to indicate that the LVD comparator has tripped, indicating that the supply voltage has gone below the trip point set by VM[2:0] (See Table 15-1). 0 = No low-voltage-detect event 1= A low-voltage-detect has tripped Bit 0: PPOR This bit is set to indicate that the PPOR comparator has tripped, indicating that the supply voltage is below the trip point set by PORLEV[1:0]. 0 = No precision-power-on-reset event 1= A precision-power-on-reset event has occurred Note This register exists in the second bank of IO space. This requires setting the XIO bit in the CPU flags register. 15.2 ECO Trim Register Table 15-3. ECO (ECO_TR) [0x1EB] [R/W] Bit # Field Read/Write Default 7 6 5 4 3 Reserved - 0 - 0 - 0 - 0 - 0 - 0 2 1 0 Sleep Duty Cycle [1:0] R/W 0 R/W 0 This register controls the ratios (in numbers of 32 kHz clock periods) of "on" time versus "off" time for LVD and POR detection circuit. Bit [7:6]: Sleep Duty Cycle [1:0] 0 0 = 1/128 periods of the Internal 32 kHz low speed oscillator. 0 1 = 1/512 periods of the Internal 32 kHz low speed oscillator. 1 0 = 1/32 periods of the Internal 32 kHz low speed oscillator. 1 1 = 1/8 periods of the Internal 32 kHz low speed oscillator. Note This register is only accessed in the second bank of IO space. This requires setting the XIO bit in the CPU flags register. Document 38-16016 Rev. *E Page 35 of 68 [+] Feedback CY7C601xx, CY7C602xx 16. General Purpose IO Ports 16.1 Port Data Registers 16.1.1 P0 Data Table 16-1. P0 Data Register (P0DATA)[0x00] [R/W] Bit # Field Read/Write Default 7 P0.7 R/W 0 6 P0.6/TIO1 R/W 0 5 P0.5/TIO0 R/W 0 4 P0.4/INT2 R/W 0 3 P0.3/INT1 R/W 0 2 P0.2/INT0 R/W 0 1 P0.1/CLKOUT R/W 0 0 P0.0/CLKIN R/W 0 This register contains the data for Port 0. Writing to this register sets the bit values to be output on output enabled pins. Reading from this register returns the current state of the Port 0 pins. Bit 7: P0.7 Data Bit [6:5]: P0.6-P0.5 Data/TIO1 and TIO0 Beside their use as the P0.6-P0.5 GPIOs, these pins are also used for alternate functions as the Capture Timer input or timer output pins (TIO1 and TIO0). To configure the P0.5 and P0.6 pins, refer to the P0.5/TIO0-P0.6/TIO1 Configuration Register (Table 16-9). Bit [4:2]: P0.4-P0.2 Data/INT2-INT0 Beside their use as the P0.4-P0.2 GPIOs, these pins are also used for the alternate functions as the interrupt pins (INT0-INT2). To configure the P0.4-P0.2 pins, refer to the P0.2/INT0-P0.4/INT2 Configuration Register (Table 16-8). Bit 1: P0.1/CLKOUT Beside its use as the P0.1 GPIO, this pin is also used for the alternate function as the CLK OUT pin. To configure the P0.1 pin, refer to the P0.1/CLKOUT Configuration Register (Table 16-7). Bit 0: P0.0/CLKIN Beside its use as the P0.0 GPIO, this pin is also used for the alternate function as the CLKIN pin. To configure the P0.0 pin, refer to the P0.0/CLKIN Configuration Register (Table 16-6). 16.1.2 P1 Data Table 16-2. P1 Data Register (P1DATA) [0x01] [R/W] Bit # Field Read/Write Default 7 P1.7 R/W 0 6 P1.6/SMISO R/W 0 5 P1.5/SMOSI R/W 0 4 P1.4/SCLK R/W 0 3 P1.3/SSEL R/W 0 2 P1.2 R/W 0 1 P1.1 R/W 0 0 P1.0 R/W 0 This register contains the data for Port 1. Writing to this register sets the bit values to be output on output enabled pins. Reading from this register returns the current state of the Port 1 pins. Bit 7: P1.7 Data Bit [6:3]: P1.6-P1.3 Data/SPI Pins (SMISO, SMOSI, SCLK, SSEL) Beside their use as the P1.6-P1.3 GPIOs, these pins are also used for the alternate function as the SPI interface pins. To configure the P1.6-P1.3 pins, refer to the P1.3-P1.6 Configuration Register (Table 16-14). Bit [2:0]: P1.2-P1.0 Document 38-16016 Rev. *E Page 36 of 68 [+] Feedback CY7C601xx, CY7C602xx 16.1.3 P2 Data Table 16-3. P2 Data Register (P2DATA) [0x02] [R/W] Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 7 6 5 P2.7-P2.2 R/W 0 R/W 0 R/W 0 R/W 0 4 3 2 1 P2.1-P2.0 R/W 0 0 This register contains the data for Port 2. Writing to this register sets the bit values to be output on output enabled pins. Reading from this register returns the current state of the Port 2 pins. Bit [7:2]: P2 Data [7:2] Bit [1:0]: P2 Data [1:0] 16.1.4 P3 Data Table 16-4. P3 Data Register (P3DATA) [0x03] [R/W] Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 7 6 5 P3.7-P3.2 R/W 0 R/W 0 R/W 0 R/W 0 4 3 2 1 P3.1-P3.0 R/W 0 0 This register contains the data for Port 3. Writing to this register sets the bit values to be output on output enabled pins. Reading from this register returns the current state of the Port 3 pins. Bit [7:2]: P3 Data [7:2] Bit [1:0]: P3 Data [1:0] 16.1.5 P4 Data Table 16-5. P4 Data Register (P4DATA) [0x04] [R/W] Bit # Field Read/Write Default - 0 - 0 7 6 Reserved - 0 - 0 R/W 0 R/W 0 5 4 3 2 P4.3-P4.0 R/W 0 R/W 0 1 0 This register contains the data for Port 4. Writing to this register sets the bit values to be output on output enabled pins. Reading from this register returns the current state of the Port 2 pins. Bit [7:4]: Reserved Bit [3:0]: P4 Data [3:0] P4.3-P4.0 only exist in the CY7C601xx. 16.2 GPIO Port Configuration All GPIO configuration registers have common configuration controls. By default all GPIOs are configured as inputs. To prevent the inputs from floating, pull up resistors are enabled. Firmware configures each of the GPIOs before use. The following are bit definitions of the GPIO configuration registers. 16.2.1 Int Enable When set, the Int Enable bit allows the GPIO to generate interrupts. Interrupt generate occurs regardless of whether the pin is configured for input or output. All interrupts are edge sensitive. However, for interrupts that are shared by multiple sources (Ports 2, 3, and 4), all inputs are deasserted before a new interrupt occurs. When clear, the corresponding interrupt is disabled on the pin. It is possible to configure GPIOs as outputs, enable the interrupt on the pin, and then generate the interrupt by driving the appropriate pin state. This is useful in test and may find value in applications as well. 16.2.2 Int Act Low When clear, the corresponding interrupt is active HIGH. When set, the interrupt is active LOW. For P0.2-P0.4 Int Act Low makes interrupts active on the rising edge. Int Act Low set makes interrupts active on the falling edge. 16.2.3 TTL Thresh When set, the input has TTL threshold. When clear, the input has standard CMOS threshold. Note The GPIOs default to CMOS threshold. User's firmware needs to configure the threshold to TTL mode if necessary. Document 38-16016 Rev. *E Page 37 of 68 [+] Feedback CY7C601xx, CY7C602xx 16.2.4 High Sink When set, the output sinks up to 50 mA. When clear, the output sinks up to 8 mA. On the CY7C601xx, only the P3.7, P2.7, P0.1, and P0.0 have 50 mA sink drive capability. Other pins have 8 mA sink drive capability. On the CY7C602xx, only the P1.7-P1.3 have 50 mA sink drive capability. Other pins have 8 mA sink drive capability. 16.2.5 Open Drain When set, the output on the pin is determined by the Port Data Register. If the corresponding bit in the Port Data Register is set, the pin is in high impedance state; if it is clear, the pin is driven LOW. When clear, the output is driven LOW or HIGH. 16.2.6 Pull Up Enable When set the pin has a 7K pull up to VDD. When clear, the pull up is disabled. Figure 16-1. GPIO Block Diagram VREG 3.3V Drive VCC 16.2.7 Output Enable When set, the output driver of the pin is enabled. When clear, the output driver of the pin is disabled. For pins with shared functions there are some special cases. P0.0(CLKIN) and P0.1(CLKOUT) are not output enabled when the crystal oscillator is enabled. Output enables for these pins are overridden by XOSC Enable. 16.2.8 SPI Use The P1.3(SSEL), P1.4(SCLK), P1.5(SMOSI), and P1.6(SMISO) pins are used for their dedicated functions or for GPIO. To enable the pin for GPIO, clear the corresponding SPI Use bit. The SPI function controls the output enable for its dedicated function pins when their GPIO enable bit is clear. Pull-Up Enable Output Enable VREG Open Drain Port Data VCC RUP Data Out GPIO PIN High Sink VREG GND Data In TTL Threshold VCC GND 16.2.9 P0.0/CLKIN Configuration Table 16-6. P0.0/CLKIN Configuration (P00CR) [0x05] [R/W] Bit # Field Read/Write Default 7 Reserved - 0 6 Int Enable R/W 0 5 Int Act Low R/W 0 4 TTL Thresh R/W 0 3 High Sink R/W 0 2 Open Drain R/W 0 1 Pull up Enable R/W 0 0 Output Enable R/W 0 This pin is shared between the P0.0 GPIO use and the CLKIN pin for the external crystal oscillator. When the external oscillator is enabled the settings of this register are ignored. The alternate function of the pin as the CLKIN is only available in the CY7C601xx. When the external oscillator is enabled (the XOSC Enable bit of the CLKIOCR Register is set--Table 12-4), the GPIO function of the pin is disabled. The 50 mA sink drive capability is only available in the CY7C601xx. In the CY7C602xx, only 8 mA sink drive capability is available on this pin regardless of the setting of the High Sink bit. Document 38-16016 Rev. *E Page 38 of 68 [+] Feedback CY7C601xx, CY7C602xx 16.2.10 P0.1/CLKOUT Configuration Table 16-7. P0.1/CLKOUT Configuration (P01CR) [0x06] R/W] Bit # Field Read/Write Default 7 CLK Output R/W 0 6 Int Enable R/W 0 5 Int Act Low R/W 0 4 TTL Thresh R/W 0 3 High Sink R/W 0 2 Open Drain R/W 0 1 Pull up Enable R/W 0 0 Output Enable R/W 0 This pin is shared between the P0.1 GPIO use and the CLKOUT pin for the external crystal oscillator. When the external oscillator is enabled the settings of this register are ignored. When CLK output is set, the internally selected clock is sent out onto P0.1CLKOUT pin. The alternate function of the pin as the CLKOUT is only available in the CY7C601xx. When the external oscillator is enabled (the XOSC Enable bit of the CLKIOCR Register is set--Table 12-4), the GPIO function of the pin is disabled. The 50 mA sink drive capability is only available in the CY7C601xx. In the CY7C602xx, only 8 mA sink drive capability is available on this pin regardless of the setting of the High Sink bit. Bit 7: CLK Output 0 = The clock output is disabled. 1 = The clock selected by the CLK Select field (Bit [1:0] of the CLKIOCR Register--Table 12-4) is driven out to the pin. 16.2.11 P0.2/INT0-P0.4/INT2 Configuration Table 16-8. P0.2/INT0-P0.4/INT2 Configuration (P02CR-P04CR) [0x07-0x09] [R/W] Bit # Field Read/Write Default 7 Reserved 6 5 Int Act Low 4 TTL Thresh R/W 0 3 Reserved 2 Open Drain R/W 0 1 Pull up Enable R/W 0 0 Output Enable R/W 0 - 0 - 0 R/W 0 - 0 These registers control the operation of pins P0.2-P0.4 respectively. These pins are shared between the P0.2-P0.4 GPIOs and the INT0-INT2. The INT0-INT2 interrupts are different from all other GPIO interrupts. These pins are connected directly to the interrupt controller to provide three edge-sensitive interrupts with independent interrupt vectors. These interrupts occur on a rising edge when Int Act Low is clear and on a falling edge when Int Act Low is set. These pins are enabled as interrupt sources in the interrupt controller registers (Table 19-8 and Table 19-6). To use these pins as interrupt inputs, configure them as inputs by clearing the corresponding Output Enable. If the INT0-INT2 pins are configured as outputs with interrupts enabled, firmware generates an interrupt by writing the appropriate value to the P0.2, P0.3, and P0.4 data bits in the P0 Data Register. Regardless of whether the pins are used as Interrupt or GPIO pins the Int Enable, Int Act Low, TTL Threshold, Open Drain, and Pull up Enable bits control the behavior of the pin. The P0.2/INT0-P0.4/INT2 pins are individually configured with the P02CR (0x07), P03CR (0x08), and P04CR (0x09) respectively. Note Changing the state of the Int Act Low bit generates an unintentional interrupt. When configuring these interrupt sources, follow this procedure: 1. Disable interrupt source 2. Configure interrupt source 3. Clear any pending interrupts from the source 4. Enable interrupt source Document 38-16016 Rev. *E Page 39 of 68 [+] Feedback CY7C601xx, CY7C602xx 16.2.12 P0.5/TIO0-P0.6/TIO1 Configuration Table 16-9. P0.5/TIO0-P0.6/TIO1 Configuration (P05CR-P06CR) [0x0A-0x0B] [R/W] Bit # Field Read/Write Default 7 TIO Output R/W 0 6 Int Enable R/W 0 5 Int Act Low R/W 0 4 TTL Thresh R/W 0 3 Reserved - 0 2 Open Drain R/W 0 1 Pull up Enable R/W 0 0 Output Enable R/W 0 These registers control the operation of pins P0.5 through P0.6, respectively. P0.5 and P0.6 are shared with TIO0 and TIO1 respectively. To use these pins as capture timer inputs, configure them as inputs by clearing the corresponding Output Enable. To use TIO0 and TIO1 as timer outputs, set the TIOx Output and Output Enable bits. If these pins are configured as outputs and the TIO Output bit is clear, firmware controls the TIO0 and TIO1 inputs by writing the value to the P0.5 and P0.6 data bits in the P0 Data Register. Regardless of whether either pin is used as a TIO or GPIO pin the Int Enable, Int Act Low, TTL Threshold, Open Drain, and Pull up Enable control the behavior of the pin. TIO0(P0.5) when enabled outputs a positive pulse from the 1024 s interval timer. This is the same signal that is used internally to generate the 1024 s timer interrupt. This signal is not gated by the interrupt enable state. The pulse is active for one cycle of the capture timer clock. TIO1(P0.6) when enabled outputs a positive pulse from the programmable interval timer. This is the same signal that is used internally to generate the programmable timer interval interrupt. This signal is not gated by the interrupt enable state.The pulse is active for one cycle of the interval timer clock. The P0.5/TIO0 and P0.6/TIO1 pins are individually configured with the P05CR (0x0A) and P06CR (0x0B), respectively. 16.2.13 P0.7 Configuration Table 16-10. P0.7 Configuration (P07CR) [0x0C] [R/W] Bit # Field Read/Write Default 7 Reserved - 0 6 Int Enable R/W 0 5 Int Act Low R/W 0 4 TTL Thresh R/W 0 3 Reserved - 0 2 Open Drain R/W 0 1 Pull up Enable R/W 0 0 Output Enable R/W 0 This register controls the operation of pin P0.7. 16.2.14 P1.0 Configuration Table 16-11. P1.0 Configuration (P10CR) [0x0D] [R/W] Bit # Field Read/Write Default 7 Reserved R/W 0 6 Int Enable R/W 0 5 Int Act Low R/W 0 - 0 4 3 Reserved - 0 - 0 2 1 P1.0 and P1.1 Pull Up Enable - 0 0 Output Enable R/W 0 This register controls the operation of the P1.0 pin. Bit1: P1.0 and P1.1 Pull Up Enable 0 = Disable the P1.0 and P1.1 pull up resistors. 1 = Enable the internal pull up resistors for both the P1.0 and P1.1. Each of the P1.0 and P1.1 pins is pulled up with RUP1 (see DC Characteristics on page 59). Note There is no 2 mA sourcing capability on this pin. The pin can only sink 5 mA at VOL3 (see DC Characteristics on page 59) The P1.0 is an open drain only output. It actively drives a signal low, but cannot actively drive a signal high. If this pin is used as a general purpose output, it draws current. It is therefore configured as an input to reduce current draw. Document 38-16016 Rev. *E Page 40 of 68 [+] Feedback CY7C601xx, CY7C602xx 16.2.15 P1.1 Configuration Table 16-12. P1.1 Configuration (P11CR) [0x0E] [R/W] Bit # Field Read/Write Default 7 Reserved - 0 6 Int Enable R/W 0 5 Int Act Low R/W 0 - 0 4 Reserved - 0 3 2 Open Drain R/W 0 1 Reserved - 0 0 Output Enable R/W 0 This register controls the operation of the P1.1 pin. The pull up resistor on this pin is enabled by the P10CR Register. Note There is no 2 mA sourcing capability on this pin. The pin can only sink 5 mA at VOL3 (see DC Characteristics on page 59) If this pin is used as a general purpose output, it draws current. It is, therefore, configured as an input to reduce current draw. 16.2.16 P1.2 Configuration Table 16-13. P1.2 Configuration (P12CR) [0x0F] [R/W] Bit # Field Read/Write Default 7 CLK Output R/W 0 6 Int Enable R/W 0 5 Int Act Low R/W 0 4 TTL Threshold R/W 0 3 Reserved - 0 2 Open Drain R/W 0 1 Pull up Enable R/W 0 0 Output Enable R/W 0 This register controls the operation of the P1.2. Bit 7: CLK Output 0 = The internally selected clock is not sent out onto P1.2 pin. 1 = This CLK Output is used to observe connected external crystal oscillator clock connected in CY7C601xx. When CLK Output is set, the internally selected clock is sent out onto P1.2 pin. Note:Table 12-4 on page 25 is used to select the external or internal clock in enCoRe II devices 16.2.17 P1.3 Configuration (SSEL) Table 16-14. P1.3 Configuration (P13CR) [0x10] [R/W] Bit # Field Read/Write Default 7 Reserved - 0 6 Int Enable R/W 0 5 Int Act Low R/W 0 4 Reserved - 0 3 High Sink R/W 0 2 Open Drain R/W 0 1 Pull Up Enable R/W 0 0 Output Enable R/W 0 This register controls the operation of the P1.3 pin. This register exists in all enCoRe II LVparts. The P1.3 GPIO's threshold is always set to TTL. When the SPI hardware is enabled or disabled, the pin is controlled by the Output Enable bit and the corresponding bit in the P1 data register. Regardless of whether the pin is used as an SPI or GPIO pin the Int Enable, Int act Low, High Sink, Open Drain, and Pull Up Enable control the behavior of the pin. Document 38-16016 Rev. *E Page 41 of 68 [+] Feedback CY7C601xx, CY7C602xx 16.2.18 P1.4-P1.6 Configuration (SCLK, SMOSI, SMISO) Table 16-15. P1.4-P1.6 Configuration (P14CR-P16CR) [0x11-0x13] [R/W] Bit # Field Read/Write Default 7 SPI Use R/W 0 6 Int Enable R/W 0 5 Int Act Low R/W 0 4 Reserved - 0 3 High Sink R/W 0 2 Open Drain R/W 0 1 Pull Up Enable R/W 0 0 Output Enable R/W 0 These registers control the operation of pins P1.4-P1.6, respectively. These registers exist in all enCoRe II LV parts. Bit 7: SPI Use 0 = Disable the SPI alternate function. The pin is used as a GPIO 1 = Enable the SPI function. The SPI circuitry controls the output of the pin The P1.4-P1.6 GPIO's threshold is always set to TTL. When the SPI hardware is enabled, pins that are configured as SPI Use have their output enable and output state controlled by the SPI circuitry. When the SPI hardware is disabled or a pin has its SPI Use bit clear, the pin is controlled by the Output Enable bit and the corresponding bit in the P1 data register. Regardless of whether any pin is used as an SPI or GPIO pin the Int Enable, Int act Low, High Sink, Open Drain, and Pull up Enable control the behavior of the pin. Note for Comm Modes 01 or 10 (SPI Master or SPI Slave, see Table 17-2 on page 45) When configured for SPI (SPI Use = 1 and Comm Modes [1:0] = SPI Master or SPI Slave mode), the input and output direction of pins P1.5, and P1.6 is set automatically by the SPI logic. However, pin P1.4's input and output direction is NOT automatically set; it must be explicitly set by firmware. For SPI Master mode, pin P1.4 must be configured as an output; for SPI Slave mode, pin P1.4 must be configured as an input. 16.2.19 P1.7 Configuration Table 16-16. P1.7 Configuration (P17CR) [0x14] [R/W] Bit # Field Read/Write Default 7 Reserved - 0 6 Int Enable R/W 0 5 Int Act Low R/W 0 4 Reserved - 0 3 High Sink R/W 0 2 Open Drain R/W 0 1 Pull Up Enable R/W 0 0 Output Enable R/W 0 This register controls the operation of pin P1.7. The 50 mA sink drive capability is only available in CY7C602xx. In CY7C601xx, only 8 mA sink drive capability is available on this pin regardless of the setting of the High Sink bit. The P1.7 GPIO's threshold is always set to TTL. 16.2.20 P2 Configuration Table 16-17. P2 Configuration (P2CR) [0x15] [R/W] Bit # Field Read/Write Default 7 Reserved - 0 6 Int Enable R/W 0 5 Int Act Low R/W 0 4 TTL Thresh R/W 0 3 High Sink R/W 0 2 Open Drain R/W 0 1 Pull Up Enable R/W 0 0 Output Enable R/W 0 In CY7C602xx, this register controls the operation of pins P2.0-P2.1. In CY7C601xx, this register controls the operation of pins P2.0-P2.7. The 50 mA sink drive capability is only available on pin P2.7 and only on CY7C601xx. In CY7C602xx, only 8 mA sink drive capability is available on this pin regardless of the setting of the High Sink bit. Document 38-16016 Rev. *E Page 42 of 68 [+] Feedback CY7C601xx, CY7C602xx 16.2.21 P3 Configuration Table 16-18. P3 Configuration (P3CR) [0x16] [R/W] Bit # Field Read/Write Default 7 Reserved - 0 6 Int Enable R/W 0 5 Int Act Low R/W 0 4 TTL Thresh R/W 0 3 High Sink R/W 0 2 Open Drain R/W 0 1 Pull Up Enable R/W 0 0 Output Enable R/W 0 In CY7C602xx, this register controls the operation of pins P3.0-P3.1. In CY7C601xx, this register controls the operation of pins P3.0-P3.7. The 50 mA sink drive capability is only available on pin P3.7 and only on CY7C601xx. In CY7C602xx, only 8 mA sink drive capability is available on this pin regardless of the setting of the High Sink bit. 16.2.22 P4 Configuration Table 16-19. P4 Configuration (P4CR) [0x17] [R/W] Bit # Field Read/Write Default 7 Reserved - 0 6 Int Enable R/W 0 5 Int Act Low R/W 0 4 TTL Thresh R/W 0 3 High Sink R/W 0 2 Open Drain R/W 0 1 Pull Up Enable R/W 0 0 Output Enable R/W 0 This register exists only in CY7C601xx. This register controls the operation of pins P4.0-P4.3. Document 38-16016 Rev. *E Page 43 of 68 [+] Feedback CY7C601xx, CY7C602xx 17. Serial Peripheral Interface (SPI) The SPI Master and Slave Interface core logic runs on the SPI clock domain. The SPI clock is a divider off of the CPUCLK when in Master Mode. SPI is a four pin serial interface comprised of a clock, an enable, and two data pins. Figure 17-1. SPI Block Diagram Register Block SCK Speed Sel SCK Clock Generation Master/Slave Sel SCK Clock Select SCK_OE SCK Polarity SCK Phase SCK Clock Phase/Polarity Select SCK SCK Little Endian Sel LE_SEL GPIO Block SS_N SS_N SPI State Machine SS_N Data (8 bit) Load Empty Master/Slave Set SCK LE_SEL Shift Buffer MISO/MOSI Crossbar Output Shift Buffer SS_N_OE MISO_OE MISO MOSI_OE MOSI Data (8 bit) Load Full Input Shift Buffer Sclk Output Enable Slave Select Output Enable Master IN, Slave Out OE Master Out, Slave In, OE SCK_OE SS_N_OE MISO_OE MOSI_OE Document 38-16016 Rev. *E Page 44 of 68 [+] Feedback CY7C601xx, CY7C602xx 17.1 SPI Data Register Table 17-1. SPI Data Register (SPIDATA) [0x3C] [R/W] Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 SPIData[7:0] R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 When read, this register returns the contents of the receive buffer. When written, it loads the transmit holding register. Bit [7:0]: SPI Data [7:0] When an interrupt occurs to indicate to firmware that a byte of receive data is available or the transmitter holding register is empty, firmware has seven SPI clocks to manage the buffers--to empty the receiver buffer or to refill the transmit holding register. Failure to meet this timing requirement results in incorrect data transfer. 17.2 SPI Configure Register Table 17-2. SPI Configure Register (SPICR) [0x3D] [R/W] Bit # Field Read/Write Default 7 Swap R/W 0 6 LSB First R/W 0 R/W 0 5 Comm Mode R/W 0 4 3 CPOL R/W 0 2 CPHA R/W 0 R/W 0 1 SCLK Select R/W 0 0 Bit 7: Swap 0 = Swap function disabled 1 = The SPI block swaps its use of SMOSI and SMISO. Among other things, this is useful to implement single wire communications similar to SPI. Bit 6: LSB First 0 = The SPI transmits and receives the MSB (Most Significant Bit) first. 1 = The SPI transmits and receives the LSB (Least Significant Bit) first. Bit [5:4]: Comm Mode [1:0] 0 0: All SPI communication disabled 0 1: SPI master mode 1 0: SPI slave mode 1 1: Reserved Bit 3: CPOL This bit controls the SPI clock (SCLK) idle polarity. 0 = SCLK idles low 1 = SCLK idles high Bit 2: CPHA The Clock Phase bit controls the phase of the clock on which data is sampled. Table 17-3 shows the timing for various combinations of LSB First, CPOL, and CPHA. Bit [1:0]: SCLK Select This field selects the speed of the master SCLK. When in master mode, SCLK is generated by dividing the base CPUCLK Important Note for Comm Modes 01b or 10b (SPI Master or SPI Slave) When configured for SPI, (SPI Use = 1 - Table 16-15), the input and output direction of pins P1.3, P1.5, and P1.6 is set automatically by the SPI logic. However, pin P1.4's input and output direction is NOT automatically set; it must be explicitly set by firmware. For SPI Master mode, pin P1.4 is configured as an output; for SPI Slave mode, pin P1.4 is configured as an input. Document 38-16016 Rev. *E Page 45 of 68 [+] Feedback CY7C601xx, CY7C602xx Table 17-3. SPI Mode Timing vs. LSB First, CPOL, and CPHA LSB First 0 CPHA CPOL 0 Diagram 0 SCLK SSEL D AT A X MSB B it 7 B it 6 B it 5 B it 4 B it 3 B it 2 LSB X 0 0 1 SC LK SSEL DAT A X MSB B it 7 B it 6 B it 5 B it 4 B it 3 B it 2 LSB X 0 1 0 SC LK SSEL DAT A 0 1 1 X MSB B it 7 B it 6 B it 5 B it 4 B it 3 B it 2 LS B X SC L K SSEL D AT A 1 0 0 X MS B B it 7 B it 6 B it 5 B it 4 B it 3 B it 2 LSB X SCLK SSEL DAT A 1 0 1 X LSB B it 2 B it 3 B it 4 B it 5 B it 6 B it 7 MS B X SCLK SSEL DAT A 1 1 0 X LSB Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 MSB X SCLK SSEL DAT A 1 1 1 X LSB Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 MSB X SC LK SSEL DAT A X LSB Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 MSB X Document 38-16016 Rev. *E Page 46 of 68 [+] Feedback CY7C601xx, CY7C602xx Table 17-4. SPI SCLK Frequency SCLK CPUCLK Select Divisor 00 01 10 11 6 12 48 96 SCLK Frequency when CPUCLK = 12 MHz 2 MHz 1 MHz 250 kHz 125 kHz 17.3 SPI Interface Pins The SPI interface uses the P1.3-P1.6 pins. These pins are configured using the P1.3 and P1.4-P1.6 configuration. 18. Timer Registers All timer functions of the enCoRe II LV are provided by a single timer block. The timer block is asynchronous from the CPU clock. The 16-bit free running counter is used as the time base for timer captures and also as a general time base by software. 18.1 Registers 18.1.1 Free Running Counter The 16-bit free running counter is clocked by the Timer Capture Clock (TCAPCLK). It is read in software for use as a general purpose time base. When reading the low order byte, the high order byte is registered. Reading the high order byte reads this register allowing the CPU to read the 16-bit value atomically (loads all bits at one time). The free running timer generates an interrupt at 1024 s rate when clocked by a 4 MHz source. It also generates an interrupt when the free running counter overflow occurs--every 16.384 ms (with a 4 MHz source). This extends the length of the timer. Figure 18-1. 16-Bit Free Running Counter Block Diagram Overflow Interrupt/W rap Interrupt Tim er Capture C lock 16-bit Free Running Counter 1024-s Tim er Interrupt Table 18-1. Free Running Timer Low Order Byte (FRTMRL) [0x20] [R/W] Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 Free Running Timer [7:0] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit [7:0]: Free Running Timer [7:0] This register holds the low order byte of the 16-bit free running timer. Reading this register moves the high order byte into a holding register allowing an automatic read of all 16 bits simultaneously. For reads, the actual read occurs in the cycle when the low order is read. For writes, the actual time the write occurs is the cycle when the high order is written. When reading the free running timer, the low order byte is read first and the high order second. When writing, the low order byte is written first then the high order byte. Document 38-16016 Rev. *E Page 47 of 68 [+] Feedback CY7C601xx, CY7C602xx Table 18-2. Free Running Timer High Order Byte (FRTMRH) [0x21] [R/W] Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 Free Running Timer [15:8] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit [7:0]: Free Running Timer [15:8] When reading the free running timer, the low order byte is read first and the high order second. When writing, the low order byte is written first, then the high order byte. 18.1.2 Time Capture enCoRe II LV has two 8-bit captures. Each capture has a separate register for rising and falling time. The two 8-bit captures can be configured as a single 16-bit capture. When configured in this way, the capture 1 registers hold the high order byte of the 16-bit timer capture value. Each of the four capture registers can be programmed to generate an interrupt when it is loaded. Figure 18-2. Time Capture Block Diagram External Clock Internal 24-MHz Oscillator Internal Low Power 32-KHz Oscillator Source Control and Configuration Timer Capture Clock Output (4-MHz Default) Programmable Interval Timer 16-bit Free Running Counter Table 18-3. Timer Configuration (TMRCR) [0x2A] [R/W] Bit # Field Read/Write Default 7 First Edge Hold R/W 0 R/W 0 6 5 8-bit Capture Prescale [2:0] R/W 0 R/W 0 4 3 Cap0 16-bit Enable R/W 0 - 0 2 1 Reserved - 0 - 0 0 Bit 7: First Edge Hold The First Edge Hold function applies to all four capture timers. 0 = The time of the most recent edge is held in the Capture Timer Data Register. If multiple edges have occurred since reading the capture timer, the time for the most recent one is read. 1 = The time of the first occurrence of an edge is held in the Capture Timer Data Register until the data is read. Subsequent edges are ignored until the Capture Timer Data Register is read. Bit [6:4]: 8-bit Capture Prescale [2:0] This field controls which eight bits of the 16 Free Running Timer are captured when in bit mode. 0 0 0 = capture timer[7:0] 0 0 1 = capture timer[8:1] 0 1 0 = capture timer[9:2] 0 1 1 = capture timer[10:3] 1 0 0 = capture timer[11:4] 1 0 1 = capture timer[12:5] 1 1 0 = capture timer[13:6] 1 1 1 = capture timer[14:7] Bit 3: Cap0 16-bit Enable 0 = Capture 0 16-bit mode is disabled 1 = Capture 0 16-bit mode is enabled. Capture 1 is disabled and the Capture 1 rising and falling registers are used as an extension to the Capture 0 registers--extending them to 16 bits. Bit [2:0]: Reserved Document 38-16016 Rev. *E Page 48 of 68 [+] Feedback CY7C601xx, CY7C602xx Table 18-4. Capture Interrupt Enable (TCAPINTE) [0x2B] [R/W] Bit # Field Read/Write Default - 0 - 0 7 6 Reserved - 0 - 0 5 4 3 Cap1 Fall Enable R/W 0 2 Cap1 Rise Enable R/W 0 1 Cap0 Fall Enable R/W 0 0 Cap0 Rise Enable R/W 0 Bit [7:4]: Reserved Bit 3: Cap1 Fall Enable 0 = Disable the capture 1 falling edge interrupt 1 = Enable the capture 1 falling edge interrupt Bit 2: Cap1 Rise Enable 0 = Disable the capture 1 rising edge interrupt 1 = Enable the capture 1 rising edge interrupt Bit 1: Cap0 Fall Enable 0 = Disable the capture 0 falling edge interrupt 1 = Enable the capture 0 falling edge interrupt Bit 0: Cap0 Rise Enable 0 = Disable the capture 0 rising edge interrupt 1 = Enable the capture 0 rising edge interrupt Table 18-5. Timer Capture 0 Rising (TCAP0R) [0x22] [R/W] Bit # Field Read/Write Default R 0 R 0 R 0 7 6 5 4 3 2 1 0 Capture 0 Rising [7:0] R 0 R 0 R 0 R 0 R 0 Bit [7:0]: Capture 0 Rising [7:0] This register holds the value of the free running timer when the last rising edge occurred on the TIO0 input. When Capture 0 is in 8-bit mode, the bits that are stored here are selected by the Prescale [2:0] bits in the Timer Configuration register. When Capture 0 is in 16-bit mode this register holds the lower order eight bits of the 16-bit timer. Table 18-6. Timer Capture 1 Rising (TCAP1R) [0x23] [R/W] Bit # Field Read/Write Default R 0 R 0 R 0 7 6 5 4 3 2 1 0 Capture 1 Rising [7:0] R 0 R 0 R 0 R 0 R 0 Bit [7:0]: Capture 1 Rising [7:0] This register holds the value of the free running timer when the last rising edge occurred on the TIO1 input. The bits that are stored here are selected by the Prescale [2:0] bits in the Timer Configuration register. When Capture 0 is in 16-bit mode this register holds the high order eight bits of the 16-bit timer from the last TIO0 rising edge. Table 18-7. Timer Capture 0 Falling (TCAP0F) [0x24] [R/W] Bit # Field Read/Write Default R 0 R 0 R 0 7 6 5 4 3 2 1 0 Capture 0 Falling [7:0] R 0 R 0 R 0 R 0 R 0 Bit [7:0]: Capture 0 Falling [7:0] This register holds the value of the free running timer when the last falling edge occurred on the TIO0 input. When Capture 0 is in 8-bit mode, the bits that are stored here are selected by the Prescale [2:0] bits in the Timer Configuration register. When Capture 0 is in 16-bit mode this register holds the lower order eight bits of the 16-bit timer. Document 38-16016 Rev. *E Page 49 of 68 [+] Feedback CY7C601xx, CY7C602xx Table 18-8. Timer Capture 1 Falling (TCAP1F) [0x25] [R/W] Bit # Field Read/Write Default R 0 R 0 R 0 7 6 5 4 3 2 1 0 Capture 1 Falling [7:0] R 0 R 0 R 0 R 0 R 0 Bit [7:0]: Capture 1 Falling [7:0] This register holds the value of the free running timer when the last falling edge occurred on the TIO1 input. The bits stored here are selected by the Prescale [2:0] bits in the Timer Configuration register. When capture 0 is in 16-bit mode this register holds the high order eight bits of the 16-bit timer from the last TIO0 falling edge. ` Table 18-9. Capture Interrupt Status (TCAPINTS) [0x2C] [R/W] Bit # Field Read/Write Default - 0 - 0 7 6 Reserved - 0 - 0 5 4 3 Cap1 Fall Active R/W 0 2 Cap1 Rise Active R/W 0 1 Cap0 Fall Active R/W 0 0 Cap0 Rise Active R/W 0 These four bits contains the status bits for the four timer captures for the four timer block capture interrupt sources. Writing any of these bits with 1 clears that interrupt. Bit [7:4]: Reserved Bit 3: Cap1 Fall Active 0 = No event 1 = A falling edge has occurred on TIO1 Bit 2: Cap1 Rise Active 0 = No event 1 = A rising edge has occurred on TIO1 Bit 1: Cap0 Fall Active 0 = No event 1 = A falling edge has occurred on TIO0 Bit 0: Cap0 Rise Active 0 = No event 1 = A rising edge has occurred on TIO0 Note The interrupt status bits are cleared by firmware to enable subsequent interrupts. This is achieved by writing a `1' to the corresponding Interrupt status bit. 18.1.3 Programmable Interval Timer Table 18-10. Programmable Interval Timer Low (PITMRL) [0x26] [R] Bit # Field Read/Write Default R 0 R 0 R 0 7 6 5 4 3 2 1 0 Prog Interval Timer [7:0] R 0 R 0 R 0 R 0 R 0 Bit [7:0]: Prog Interval Timer [7:0] This register holds the low order byte of the 12-bit programmable interval timer. Reading this register moves the high order byte into a holding register allowing an automatic read of all 12 bits simultaneously. Document 38-16016 Rev. *E Page 50 of 68 [+] Feedback CY7C601xx, CY7C602xx Table 18-11. Programmable Interval Timer High (PITMRH) [0x27] [R] Bit # Field Read/Write Default -0 -0 7 6 Reserved -0 -0 R 0 5 4 3 2 1 0 Prog Interval Timer [11:8] R 0 R 0 R 0 Bit [7:4]: Reserved Bit [3:0]: Prog Internal Timer [11:8] This register holds the high order nibble of the 12-bit programmable interval timer. Reading this register returns the high order nibble of the 12-bit timer at the instant when the low order byte was last read. Table 18-12. Programmable Interval Reload Low (PIRL) [0x28] [R/W] Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 Prog Interval [7:0] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit [7:0]: Prog Interval [7:0] This register holds the lower eight bits of the timer. When writing into the 12-bit reload register, write lower byte first then the higher nibble. Table 18-13. Programmable Interval Reload High (PIRH) [0x29] [R/W] Bit # Field Read/Write Default -0 -0 7 6 Reserved -0 -0 R/W 0 5 4 3 2 1 0 Prog Interval[11:8] R/W 0 R/W 0 R/W 0 Bit [7:4]: Reserved Bit [3:0]: Prog Interval [11:8] This register holds the higher 4 bits of the timer. When writing into the 12-bit reload register, write lower byte first then the higher nibble. Document 38-16016 Rev. *E Page 51 of 68 [+] Feedback CY7C601xx, CY7C602xx Figure 18-3. Timer Functional Sequence Diagram Document 38-16016 Rev. *E Page 52 of 68 [+] Feedback CY7C601xx, CY7C602xx Figure 18-4. 16-Bit Free Running Counter Loading Timing Diagram clk_sys write valid addr write data FRT reload ready Clk Timer 12b Prog Timer 12b reload interrupt 12-bit programmable timer load timing Capture timer clk 16b free running counter load 16b free running counter 00A0 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 00A9 00AB 00AC 00AD 00AE 00AF 00B0 00B1 00B2 ACBE ACBF ACC0 16-bit free running counter loading timing Figure 18-5. Memory Mapped Registers Read and Write Timing Diagram clk_sys rd_wrn Valid Addr rdata wdata Memory mapped registers Read/Write timing diagram Document 38-16016 Rev. *E Page 53 of 68 [+] Feedback CY7C601xx, CY7C602xx 19. Interrupt Controller The interrupt controller and its associated registers allow the user's code to respond to an interrupt from almost every functional block in the enCoRe II LV devices. The registers associated with the interrupt controller are disabled either globally or individually. The registers also provide a mechanism for users to clear all pending and posted interrupts or clear individual posted or pending interrupts. Table 19-1 lists all interrupts and the priorities that are available in the enCoRe II LV devices. Table 19-1. Interrupt Priorities, Address, and Name Interrupt Priority 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Interrupt Address 0000h 0004h 0008h 000Ch 0010h 0014h 0018h 001Ch 0020h 0024h 0028h 002Ch 0030h 0034h 0038h 003Ch Reset POR/LVD INT0 SPI Transmitter Empty SPI Receiver Full GPIO Port 0 GPIO Port 1 INT1 Reserved Reserved Reserved Reserved Reserved 1 mS Interval timer Programmable Interval Timer Timer Capture 0 Name Table 19-1. Interrupt Priorities, Address, and Name (continInterrupt Priority 16 17 18 19 20 21 22 23 24 25 Interrupt Address 0040h 0044h 0048h 004Ch 0050h 0054h 0058h 005Ch 0060h 0064h Name Timer Capture 1 16-bit Free Running Timer Wrap INT2 Reserved GPIO Port 2 GPIO Port 3 GPIO Port 4 Reserved Reserved Sleep Timer 19.1 Architectural Description An interrupt is posted when its interrupt conditions occur. This results in the flip-flop in Figure 19-1. clocking in a `1'. The interrupt remains posted until the interrupt is taken or until it is cleared by writing to the appropriate INT_CLRx register. A posted interrupt is not pending unless it is enabled by setting its interrupt mask bit (in the appropriate INT_MSKx register). All pending interrupts are processed by the Priority Encoder to determine the highest priority interrupt which is taken by the M8C if the Global Interrupt Enable bit is set in the CPU_F register. Disabling an interrupt by clearing its interrupt mask bit (in the INT_MSKx register) does not clear a posted interrupt, nor does it prevent an interrupt from being posted. It simply prevents a posted interrupt from becoming pending. Nested interrupts are accomplished by reenabling interrupts inside an interrupt service routine. To do this, set the IE bit in the Flag Register. A block diagram of the enCoRe II LV Interrupt Controller is shown in Figure 19-1.. Figure 19-1. Interrupt Controller Block Diagram Interrupt Taken or INT_CLRx Write Posted Interrupt Pending Interrupt Priority Encoder Interrupt Vector Interrupt Request M8C Core R 1 Interrupt Source (Timer, GPIO, etc.) INT_MSKx Mask Bit Setting D Q ... ... CPU_F[0] GIE Document 38-16016 Rev. *E Page 54 of 68 [+] Feedback CY7C601xx, CY7C602xx 19.2 Interrupt Processing The sequence of events that occur during interrupt processing is as follows: 1. An interrupt becomes active, either because: a. The interrupt condition occurs (for example, a timer expires). b. A previously posted interrupt is enabled through an update of an interrupt mask register. c. An interrupt is pending and GIE is set from 0 to 1 in the CPU Flag register. 2. The current executing instruction finishes. 3. The internal interrupt is dispatched, taking 13 cycles. During this time, the following actions occur: a. The MSB and LSB of Program Counter and Flag registers (CPU_PC and CPU_F) are stored onto the program stack by an automatic CALL instruction (13 cycles) generated during the interrupt acknowledge process. b. The PCH, PCL, and Flag register (CPU_F) are stored onto the program stack (in that order) by an automatic CALL instruction (13 cycles) generated during the interrupt acknowledge process. c. The CPU_F register is then cleared. Since this clears the GIE bit to 0, additional interrupts are temporarily disabled. d. The PCH (PC[15:8]) is cleared to zero. e. The interrupt vector is read from the interrupt controller and its value placed into PCL (PC[7:0]). This sets the program counter to point to the appropriate address in the interrupt table (for example, 0004h for the POR and LVD interrupt). 4. Program execution vectors to the interrupt table. Typically, a LJMP instruction in the interrupt table sends execution to the user's Interrupt Service Routine (ISR) for this interrupt. 5. The ISR executes. Note that interrupts are disabled since GIE = 0. In the ISR, interrupts are re-enabled if desired, by setting GIE = 1 (avoid stack overflow). Table 19-2. Interrupt Clear 0 (INT_CLR0) [0xDA] [R/W] Bit # Field Read/Write Default 7 GPIO Port 1 R/W 0 6 Sleep Timer R/W 0 5 INT1 R/W 0 4 GPIO Port 0 R/W 0 6. The ISR ends with a RETI instruction which restores the Program Counter and Flag registers (CPU_PC and CPU_F). The restored Flag register re-enables interrupts, since GIE = 1 again. 7. Execution resumes at the next instruction, after the one that occurred before the interrupt. However, if there are more pending interrupts, the subsequent interrupts are processed before the next normal program instruction. 19.3 Interrupt Latency The time between the assertion of an enabled interrupt and the start of its ISR is calculated from the following equation. Latency = Time for current instruction to finish + Time for internal interrupt routine to execute + Time for LJMP instruction in interrupt table to execute. For example, if the 5 cycle JMP instruction is executing when an interrupt becomes active, the total number of CPU clock cycles before the ISR begins is as follows: (1 to 5 cycles for JMP to finish) + (13 cycles for interrupt routine) + (7 cycles for LJMP) = 21 to 25 cycles. In the example above, at 12 MHz, 25 clock cycles take 2.08 s. 19.4 Interrupt Registers 19.4.1 Interrupt Clear Register The Interrupt Clear Registers (INT_CLRx) are used to enable the individual interrupt sources' ability to clear posted interrupts. When an INT_CLRx register is read, any bits that are set indicates an interrupt has been posted for that hardware resource. Therefore, reading these registers gives the user the ability to determine all posted interrupts. 3 SPI Receive R/W 0 2 SPI Transmit R/W 0 1 INT0 R/W 0 0 POR/LVD R/W 0 When reading this register, 0 = There is no posted interrupt for the corresponding hardware. 1 = There is a posted interrupt for the corresponding hardware. Writing a `0' to the bits clears the posted interrupts for the corresponding hardware. Writing a `1' to the bits and to the ENSWINT (Bit 7 of the INT_MSK3 Register) posts the corresponding hardware interrupt. The GPIO interrupts are edge-triggered. Document 38-16016 Rev. *E Page 55 of 68 [+] Feedback CY7C601xx, CY7C602xx Table 19-3. Interrupt Clear 1 (INT_CLR1) [0xDB] [R/W] Bit # Field Read/Write Default 7 TCAP0 R/W 0 6 Prog Interval Timer R/W 0 5 1-ms Programmable Interrupt R/W 0 - 0 - 0 4 3 2 Reserved - 0 - 0 - 0 1 0 When reading this register, 0 = There is no posted interrupt for the corresponding hardware. 1 = There is a posted interrupt for the corresponding hardware. Writing a `0' to the bits clears the posted interrupts for the corresponding hardware. Writing a `1' to the bits AND to the ENSWINT (Bit 7 of the INT_MSK3 Register) posts the corresponding hardware interrupt. Table 19-4. Interrupt Clear 2 (INT_CLR2) [0xDC] [R/W] Bit # Field Read/Write Default 7 Reserved - 0 6 GPIO Port 4 R/W 0 5 GPIO Port 3 R/W 0 4 GPIO Port 2 R/W 0 3 Reserved - 0 2 INT2 R/W 0 1 16-bit Counter Wrap R/W 0 0 TCAP1 R/W 0 When reading this register, 0 = There is no posted interrupt for the corresponding hardware. 1 = There is a posted interrupt for the corresponding hardware. Writing a `0' to the bits clears the posted interrupts for the corresponding hardware. Writing a `1' to the bits AND to the ENSWINT (Bit 7 of the INT_MSK3 Register) posts the corresponding hardware interrupt. 19.4.2 Interrupt Mask Registers The Interrupt Mask Registers (INT_MSKx) enable the individual interrupt sources' ability to create pending interrupts. There are four Interrupt Mask Registers (INT_MSK0, INT_MSK1, INT_MSK2, and INT_MSK3) which are referred to in general as INT_MSKx. If cleared, each bit in an INT_MSKx register prevents a posted interrupt from becoming a pending interrupt (input to the priority encoder). However, an interrupt can still post even if its mask bit is zero. All INT_MSKx bits are independent of all other INT_MSKx bits. If an INT_MSKx bit is set, the interrupt source associated with that mask bit generates an interrupt that becomes a pending interrupt. Table 19-5. Interrupt Mask 3 (INT_MSK3) [0xDE] [R/W] Bit # Field Read/Write Default 7 ENSWINT R 0 - 0 - 0 - 0 6 5 4 3 Reserved - 0 - 0 - 0 - 0 2 1 0 The Enable Software Interrupt (ENSWINT) bit in INT_MSK3[7] determines the way an individual bit value written to an INT_CLRx register is interpreted. When cleared, writing 1s to an INT_CLRx register has no effect. However, writing 0s to an INT_CLRx register, when ENSWINT is cleared, causes the corresponding interrupt to clear. If the ENSWINT bit is set, 0s written to the INT_CLRx registers are ignored. However, 1s written to an INT_CLRx register, when ENSWINT is set, causes an interrupt to post for the corresponding interrupt. Software interrupts aid in debugging interrupt service routines by eliminating the need to create system level interactions that are sometimes necessary to create a hardware only interrupt. Bit 7: Enable Software Interrupt (ENSWINT) 0= Disable. Writing 0s to an INT_CLRx register, when ENSWINT is cleared, clears the corresponding interrupt. 1= Enable. Writing 1s to an INT_CLRx register, when ENSWINT is set, posts the corresponding interrupt. Bit [6:0]: Reserved Document 38-16016 Rev. *E Page 56 of 68 [+] Feedback CY7C601xx, CY7C602xx Table 19-6. Interrupt Mask 2 (INT_MSK2) [0xDF] [R/W] Bit # Field Read/Write Default 7 Reserved - 0 6 GPIO Port 4 Int Enable R/W 0 5 GPIO Port 3 Int Enable R/W 0 4 GPIO Port 2 Int Enable R/W 0 3 Reserved - 0 2 INT2 Int Enable R/W 0 1 16-bit Counter Wrap Int Enable R/W 0 0 TCAP1 Int Enable R/W 0 Bit 7: Reserved Bit 6: GPIO Port 4 Interrupt Enable 0 = Mask GPIO Port 4 interrupt 1 = Unmask GPIO Port 4 interrupt Bit 5: GPIO Port 3 Interrupt Enable 0 = Mask GPIO Port 3 interrupt 1 = Unmask GPIO Port 3 interrupt Bit 4: GPIO Port 2 Interrupt Enable 0 = Mask GPIO Port 2 interrupt 1 = Unmask GPIO Port 2 interrupt Bit 3: Reserved Bit 2: INT2 Interrupt Enable 0 = Mask INT2 interrupt 1 = Unmask INT2 interrupt Bit 1: 16-bit Counter Wrap Interrupt Enable 0 = Mask 16-bit Counter Wrap interrupt 1 = Unmask 16-bit Counter Wrap interrupt Bit 0: TCAP1 Interrupt Enable 0 = Mask TCAP1 interrupt 1 = Unmask TCAP1 interrupt The GPIO interrupts are edge-triggered. Table 19-7. Interrupt Mask 1 (INT_MSK1) [0xE1] [R/W] Bit # Field 7 TCAP0 Int Enable R/W 0 6 Prog Interval Timer Int Enable R/W 0 5 1-ms Timer Int Enable R/W 0 - 0 - 0 4 3 2 Reserved 1 0 Read/Write Default - 0 - 0 - 0 Bit 7: TCAP0 Interrupt Enable 0 = Mask TCAP0 interrupt 1 = Unmask TCAP0 interrupt Bit 6: Prog Interval Timer Interrupt Enable 0 = Mask Prog Interval Timer interrupt 1 = Unmask Prog Interval Timer interrupt Bit 5: 1 ms Timer Interrupt Enable 0 = Mask 1 ms interrupt 1 = Unmask 1 ms interrupt Bit [4:0]: Reserved Document 38-16016 Rev. *E Page 57 of 68 [+] Feedback CY7C601xx, CY7C602xx Table 19-8. Interrupt Mask 0 (INT_MSK0) [0xE0] [R/W] Bit # Field Read/Write Default 7 GPIO Port 1 Int Enable R/W 0 6 Sleep Timer Int Enable R/W 0 5 INT1 Int Enable R/W 0 4 GPIO Port 0 Int Enable R/W 0 3 SPI Receive Int Enable R/W 0 2 SPI Transmit Int Enable R/W 0 1 INT0 Int Enable R/W 0 0 POR/LVD Int Enable R/W 0 Bit 7: GPIO Port 1 Interrupt Enable 0 = Mask GPIO Port 1 interrupt 1 = Unmask GPIO Port 1 interrupt Bit 6: Sleep Timer Interrupt Enable 0 = Mask Sleep Timer interrupt 1 = Unmask Sleep Timer interrupt Bit 5: INT1 Interrupt Enable 0 = Mask INT1 interrupt 1 = Unmask INT1 interrupt Bit 4: GPIO Port 0 Interrupt Enable 0 = Mask GPIO Port 0 interrupt 1 = Unmask GPIO Port 0 interrupt Bit 3: SPI Receive Interrupt Enable 0 = Mask SPI Receive interrupt 1 = Unmask SPI Receive interrupt Bit 2: SPI Transmit Enable 0 = Mask SPI Transmit interrupt 1 = Unmask SPI Transmit interrupt Bit 1: INT0 Interrupt Enable 0 = Mask INT0 interrupt 1 = Unmask INT0 interrupt Bit 0: POR/LVD Interrupt Enable 0 = Mask POR/LVD interrupt 1 = Unmask POR/LVD interrupt 19.4.3 Interrupt Vector Clear Register Table 19-9. Interrupt Vector Clear Register (INT_VC) [0xE2] [R/W] Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 Pending Interrupt [7:0] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 The Interrupt Vector Clear Register (INT_VC) holds the interrupt vector for the highest priority pending interrupt when read, and when written clears all pending interrupts. Bit [7:0]: Pending Interrupt [7:0] 8-bit data value holds the interrupt vector for the highest priority pending interrupt. Writing to this register clears all pending interrupts. Note 4. Available only on CY7C601xx P2.7, P3.7, P0.0, P0.1; CY7C602xx P1.3,P1.4,P1.5,P1.6,P1.7. Document 38-16016 Rev. *E Page 58 of 68 [+] Feedback CY7C601xx, CY7C602xx 20. Absolute Maximum Ratings Storage Temperature ................................... -40C to +90C Ambient Temperature with Power Applied..... -0C to +70C Supply Voltage on VCC Relative to VSS ..........-0.5V to +7.0V DC Input Voltage ............................... -0.5V to + VCC + 0.5V DC Voltage Applied to Outputs in High-Z State....................................... -0.5V to + VCC + 0.5V Maximum Total Sink Output Current into Port 0 and 1 and Pins............................................................. 70 mA Maximum Total Source Output Current into GPIO Pins30 mA Maximum On-chip Power Dissipation on any GPIO Pin......................................................... 50 mW Power Dissipation .................................................... 300 mW Static Discharge Voltage ............................................. 2200V Latch-up Current ...................................................... 200 mA 20.1 DC Characteristics Parameter VCC1 TFP ICC1 Description General Operating Voltage Operating Temperature VCC Operating Supply Current Conditions CPU speed <= 12 MHz Flash programming CPU =12 MHz, Vdd = 3.3V, T = 75C CPU =12 MHz, Vdd = 2.7V, T = 25C ICC2 VCC Operating Supply Current CPU = 6 MHz, Vdd = 3.3V, T = 75C CPU = 6 MHz, Vdd = 3.3V, T = 25C ICC3 ISB1 VCC Operating Supply Current Standby Current CPU = 3 MHz, Vdd = 2.7V, T = 25C Internal and external oscillators, Bandgap, Flash, CPU clock, timer clock all disabled LVDCR [2:0] set to 000 2.681 4 Low to high edge High to low edge 40% 30% 3% 1.6 IOL1 = 50 mA IOL1 = 25 mA IOL2 = 8 mA IOH = 2 mA VCC - 0.5 1.4 0.4 0.8 Min 2.7 0 4.25 3.25 3.15 2.45 2.0 Typical Max 3.6 70 11 9 10 Unit V C mA mA mA mA mA A Low Voltage Detect VLVD RUP VICR VICF VHC VILTTL VIHTTL VOL1 VOL2 VOL3 VOH Low Voltage Detect Trip Voltage Pull Up Resistance Input Threshold Voltage Low, CMOS Mode Input Threshold Voltage Low, CMOS Mode Input Low Voltage, TTL Mode Input HIGH Voltage, TTL Mode Output Low Voltage, High Drive[4] Output Low Voltage, High Drive[4] Output Low Voltage, Low Drive Output High Voltage[4] 2.7 12 65% 55% 10% 0.72 V K VCC VCC VCC V V V V V V General Purpose IO Interface Input Hysteresis Voltage, CMOS Mode High to low edge Notes 5. Refer to Clocking on page 21 for details on loading proper trim values. 6. In Master mode first bit is available 0.5 SPICLK cycle before Master clock edge available on the SCLK pin. Document 38-16016 Rev. *E Page 59 of 68 [+] Feedback CY7C601xx, CY7C602xx 20.2 AC Characteristics Parameter Clock TECLKDC TECLK2 FIMO FILO TR_GPIO TF_GPIO SPI Timing TSMCK TSSCK TSCKH TSCKL TMDO TMDO1 TMSU TMHD TSSU TSHD TSDO TSDO1 TSSS TSSH SPI Master Clock Rate SPI Slave Clock Rate SPI Clock High Time SPI Clock Low Time Master Data Output Time[6] Master Data Output Time, First bit with CPHA = 0 Master Input Data Setup time Master Input Data Hold time Slave Input Data Setup Time Slave Input Data Hold Time Slave Data Output Time Slave Data Output Time, First bit with CPHA = 0 Slave Select Setup Time Slave Select Hold Time SCK to data valid Time after SS LOW to data valid Before first SCK edge After last SCK edge Figure 20-1. Clock Timing TCYC TCH 150 150 High for CPOL = 0, Low for CPOL = 1 Low for CPOL = 0, High for CPOL = 1 SCK to data valid Time before leading SCK edge 125 125 -25 100 50 50 50 50 100 100 50 FCPUCLK/6 2 2.2 MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns External Clock Duty Cycle External Clock Frequency Internal Main Oscillator Frequency Internal Low Power Oscillator Output Rise Time Output Fall Time With proper trim values loaded[5] With proper trim values loaded[5] Measured between 10 and 90% Vdd and Vreg with 50 pF load Measured between 10 and 90% Vdd and Vreg with 50 pF load 45 1 18.72 15.0001 55 24 26.4 50.0 50 15 % MHz MHz KHz ns ns Description Conditions Min Typical Max Unit GPIO Timing CLOCK TCL Document 38-16016 Rev. *E Page 60 of 68 [+] Feedback CY7C601xx, CY7C602xx Figure 20-2. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TR_GPIO TF_GPIO Figure 20-3. SPI Master Timing, CPHA = 1 SS (SS is under firmware control in SPI Master mode) TSCKL SCK (CPOL=0) TSCKH SCK (CPOL=1) TMDO MOSI MSB LSB MISO MSB LSB TMSU TMHD Document 38-16016 Rev. *E Page 61 of 68 [+] Feedback CY7C601xx, CY7C602xx Figure 20-4. SPI Slave Timing, CPHA = 1 SS TSSS TSCKL TSSH TSCKH SCK (CPOL=0) SCK (CPOL=1) MOSI TSDO MSB LSB TSSU TSHD MSB LSB MISO Figure 20-5. SPI Master Timing, CPHA = 0 SS (SS is under firmware control in SPI Master mode) TSCKL SCK (CPOL=0) TSCKH SCK (CPOL=1) TMDO1 TMDO MSB LSB MOSI MISO MSB LSB TMSU TMHD Document 38-16016 Rev. *E Page 62 of 68 [+] Feedback CY7C601xx, CY7C602xx Figure 20-6. SPI Slave Timing, CPHA = 0 SS TSSS TSCKL TSSH TSCKH SCK (CPOL=0) SCK (CPOL=1) MOSI MSB LSB TSSU TSHD TSDO1 TSDO MSB LSB MISO 1 21. Ordering Information Ordering Code CY7C60123-PVXC CY7C60123-PXC CY7C60113-PVXC CY7C60223-PXC CY7C60223-SXC CY7C60223-QXC FLASH Size 8K 8K 8K 8K 8K 8K RAM Size 256 256 256 256 256 256 48-SSOP 40-PDIP 28-SSOP 24-PDIP 24-SOIC 24-QSOP Package Type 22. Package Handling Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving the factory. A label on the packaging has details about actual bake temperature and the minimum bake time to remove this moisture. The maximum bake time is the aggregate time that the parts are exposed to the bake temperature. Exceeding this exposure time may degrade device reliability. Parameter TBAKETEMP TBAKETIME Description Bake Temperature Bake Time See package label Min Typical 125 Max See package label 72 Unit C hours Document 38-16016 Rev. *E Page 63 of 68 [+] Feedback CY7C601xx, CY7C602xx 23. Package Diagrams Figure 23-1. 24-Pin (300-Mil) SOIC S13 NOTE : PIN 1 ID 1. JEDEC STD REF MO-119 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE. 12 1 MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE 3. DIMENSIONS IN INCHES 0.291[7.391] 0.300[7.620] MIN. MAX. 4. PACKAGE WEIGHT 0.65gms * 0.394[10.007] 0.419[10.642] 13 24 0.026[0.660] 0.032[0.812] PART # S24.3 STANDARD PKG. SZ24.3 LEAD FREE PKG. SEATING PLANE 0.597[15.163] 0.615[15.621] 0.092[2.336] 0.105[2.667] * 0.050[1.270] TYP. 0.004[0.101] 0.0118[0.299] 0.013[0.330] 0.019[0.482] 0.004[0.101] 0.015[0.381] 0.050[1.270] * 0.0091[0.231] 0.0125[0.317] 51-85025 *C Figure 23-2. 24-Pin (300-Mil) PDIP P13 51-85013-*B Document 38-16016 Rev. *E Page 64 of 68 [+] Feedback CY7C601xx, CY7C602xx Figure 23-3. 24-Pin QSOP O241 0.033 REF. 12 1 PIN 1 ID 0.228 0.244 0.150 0.157 DIMENSIONS IN INCHES MIN. MAX. 13 24 0.337 0.344 SEATING PLANE 0.053 0.069 0.004 0.007 0.010 0.004 0.010 0.008 0.012 0.025 BSC. 0.016 0.034 0-8 51-85055-*B Figure 23-4. 28-Pin (5.3 mm) Shrunk Small Outline Package O28 51-85079-*C Document 38-16016 Rev. *E Page 65 of 68 [+] Feedback CY7C601xx, CY7C602xx Figure 23-5. 40-Pin (600-Mil) Molded DIP P17 51-85019-*A Figure 23-6. 48-Pin Shrunk Small Outline Package O48 51-85061-*C Document 38-16016 Rev. *E Page 66 of 68 [+] Feedback CY7C601xx, CY7C602xx 24. Document History Page Document Title: CY7C601xx, CY7C602xx enCoReTM II Low Voltage Microcontroller Document Number: 38-16016 Rev. ** *A ECN 327601 400134 Orig. of Change BON BHA Submission Date See ECN See ECN New data sheet Updated Power consumption values Corrected Pin Assignment Table for 24 QSOP, 24 PDIP and 28 SSOP packages Minor text changes for clarification purposes Corrected INT_MSK0 and INT_MSK1 register address Corrected register bit definitions Corrected Protection Mode Settings in Table 10-7 Updated LVD Trip Point values Added Block diagrams for Timer functional timing Replaced TBD's with actual values Added SPI Block Diagram Added Timing Block Diagrams Removed CY7C60123 DIE from Figure 5-1 Removed CY7C60123-WXC from Section 22.0 Ordering Information Updated internal 24 MHz oscillator accuracy information Added information on sending/receiving data when using 32 KHz oscillator Minor text changes GPIO capacitance and timing diagram included Method to clear Capture Interrupt Status bit discussed Sleep and Wakeup sequence documented PIT Timer registers' R/W capability corrected to read only Modified Free Running Counter text in section 17.1.1 Change title from Wireless enCoRe II to enCoRe II Low Voltage Changed "High current drive" on GPIO pins to "2 mA source current on all GPIO pins". Changed the storage temperature from -40C to 90C in "Absolute Maximum ratings" section. Added the line "The GPIOs interrupts are edge-triggered." in Tables 19-2 and 19-6. Made timing changes in Table 43. Added Figure 12-1 (SROM Table) and text after it. Also modified Table 12-1 based on Figure 12-1 (SROM Table). Changed "CAPx" to "TIOx" in Tables 18-8 and 18-9. Changed "Capturex" to "TIOx" in Figure 18-3. Added Package Handling information Formatted code in Clocking section, Removed reference to external crystal oscillator in Tables 12-2 and 12-4 Description of Change *B 505222 TYJ See ECN *C *D 524104 1821746 KKVTMP VGT/FSU/AES A See ECN See ECN *E 2620679 CMCC/PYRS 12/12/08 Document 38-16016 Rev. *E Page 67 of 68 [+] Feedback CY7C601xx, CY7C602xx Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb (c) Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document 38-16016 Rev. *E Revised December 08, 2008 Page 68 of 68 PSoC is a registered trademark and enCoRe is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback |
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